Lines Matching +full:segment +full:- +full:no +full:- +full:remap
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
49 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
51 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
75 if (drhd->include_all) in dmar_register_drhd_unit()
76 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
78 list_add_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
88 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || in dmar_alloc_dev_scope()
89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || in dmar_alloc_dev_scope()
90 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_alloc_dev_scope()
92 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && in dmar_alloc_dev_scope()
93 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { in dmar_alloc_dev_scope()
96 start += scope->length; in dmar_alloc_dev_scope()
134 if (pci_domain_nr(dev->bus) > U16_MAX) in dmar_alloc_pci_notify_info()
139 for (tmp = dev; tmp; tmp = tmp->bus->self) in dmar_alloc_pci_notify_info()
149 dmar_dev_scope_status = -ENOMEM; in dmar_alloc_pci_notify_info()
154 info->event = event; in dmar_alloc_pci_notify_info()
155 info->dev = dev; in dmar_alloc_pci_notify_info()
156 info->seg = pci_domain_nr(dev->bus); in dmar_alloc_pci_notify_info()
157 info->level = level; in dmar_alloc_pci_notify_info()
159 for (tmp = dev; tmp; tmp = tmp->bus->self) { in dmar_alloc_pci_notify_info()
160 level--; in dmar_alloc_pci_notify_info()
161 info->path[level].bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
162 info->path[level].device = PCI_SLOT(tmp->devfn); in dmar_alloc_pci_notify_info()
163 info->path[level].function = PCI_FUNC(tmp->devfn); in dmar_alloc_pci_notify_info()
164 if (pci_is_root_bus(tmp->bus)) in dmar_alloc_pci_notify_info()
165 info->bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
183 if (info->bus != bus) in dmar_match_pci_path()
185 if (info->level != count) in dmar_match_pci_path()
189 if (path[i].device != info->path[i].device || in dmar_match_pci_path()
190 path[i].function != info->path[i].function) in dmar_match_pci_path()
201 i = info->level - 1; in dmar_match_pci_path()
202 if (bus == info->path[i].bus && in dmar_match_pci_path()
203 path[0].device == info->path[i].device && in dmar_match_pci_path()
204 path[0].function == info->path[i].function) { in dmar_match_pci_path()
205 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", in dmar_match_pci_path()
213 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
215 void *start, void*end, u16 segment, in dmar_insert_dev_scope() argument
220 struct device *tmp, *dev = &info->dev->dev; in dmar_insert_dev_scope()
224 if (segment != info->seg) in dmar_insert_dev_scope()
227 for (; start < end; start += scope->length) { in dmar_insert_dev_scope()
229 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
230 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_insert_dev_scope()
234 level = (scope->length - sizeof(*scope)) / sizeof(*path); in dmar_insert_dev_scope()
235 if (!dmar_match_pci_path(info, scope->bus, path, level)) in dmar_insert_dev_scope()
244 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch in dmar_insert_dev_scope()
247 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
248 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || in dmar_insert_dev_scope()
249 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && in dmar_insert_dev_scope()
250 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in dmar_insert_dev_scope()
251 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { in dmar_insert_dev_scope()
253 pci_name(info->dev)); in dmar_insert_dev_scope()
254 return -EINVAL; in dmar_insert_dev_scope()
259 devices[i].bus = info->dev->bus->number; in dmar_insert_dev_scope()
260 devices[i].devfn = info->dev->devfn; in dmar_insert_dev_scope()
266 return -EINVAL; in dmar_insert_dev_scope()
272 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, in dmar_remove_dev_scope() argument
278 if (info->seg != segment) in dmar_remove_dev_scope()
282 if (tmp == &info->dev->dev) { in dmar_remove_dev_scope()
299 if (dmaru->include_all) in dmar_pci_bus_add_dev()
302 drhd = container_of(dmaru->hdr, in dmar_pci_bus_add_dev()
305 ((void *)drhd) + drhd->header.length, in dmar_pci_bus_add_dev()
306 dmaru->segment, in dmar_pci_bus_add_dev()
307 dmaru->devices, dmaru->devices_cnt); in dmar_pci_bus_add_dev()
327 if (dmar_remove_dev_scope(info, dmaru->segment, in dmar_pci_bus_del_dev()
328 dmaru->devices, dmaru->devices_cnt)) in dmar_pci_bus_del_dev()
337 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev)); in vf_inherit_msi_domain()
349 if (pdev->is_virtfn) { in dmar_pci_bus_notifier()
395 if (dmaru->segment == drhd->segment && in dmar_find_dmaru()
396 dmaru->reg_base_addr == drhd->address) in dmar_find_dmaru()
403 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
418 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); in dmar_parse_one_drhd()
420 return -ENOMEM; in dmar_parse_one_drhd()
426 dmaru->hdr = (void *)(dmaru + 1); in dmar_parse_one_drhd()
427 memcpy(dmaru->hdr, header, header->length); in dmar_parse_one_drhd()
428 dmaru->reg_base_addr = drhd->address; in dmar_parse_one_drhd()
429 dmaru->segment = drhd->segment; in dmar_parse_one_drhd()
431 dmaru->reg_size = 1UL << (drhd->size + 12); in dmar_parse_one_drhd()
432 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ in dmar_parse_one_drhd()
433 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), in dmar_parse_one_drhd()
434 ((void *)drhd) + drhd->header.length, in dmar_parse_one_drhd()
435 &dmaru->devices_cnt); in dmar_parse_one_drhd()
436 if (dmaru->devices_cnt && dmaru->devices == NULL) { in dmar_parse_one_drhd()
438 return -ENOMEM; in dmar_parse_one_drhd()
443 dmar_free_dev_scope(&dmaru->devices, in dmar_parse_one_drhd()
444 &dmaru->devices_cnt); in dmar_parse_one_drhd()
459 if (dmaru->devices && dmaru->devices_cnt) in dmar_free_drhd()
460 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); in dmar_free_drhd()
461 if (dmaru->iommu) in dmar_free_drhd()
462 free_iommu(dmaru->iommu); in dmar_free_drhd()
472 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { in dmar_parse_one_andd()
474 "Your BIOS is broken; ANDD object name is not NUL-terminated\n" in dmar_parse_one_andd()
480 return -EINVAL; in dmar_parse_one_andd()
482 pr_info("ANDD device: %x name: %s\n", andd->device_number, in dmar_parse_one_andd()
483 andd->device_name); in dmar_parse_one_andd()
496 if (drhd->reg_base_addr == rhsa->base_address) { in dmar_parse_one_rhsa()
497 int node = pxm_to_node(rhsa->proximity_domain); in dmar_parse_one_rhsa()
501 drhd->iommu->node = node; in dmar_parse_one_rhsa()
506 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" in dmar_parse_one_rhsa()
508 rhsa->base_address, in dmar_parse_one_rhsa()
529 switch (header->type) { in dmar_table_print_dmar_entry()
534 (unsigned long long)drhd->address, drhd->flags); in dmar_table_print_dmar_entry()
540 (unsigned long long)rmrr->base_address, in dmar_table_print_dmar_entry()
541 (unsigned long long)rmrr->end_address); in dmar_table_print_dmar_entry()
545 pr_info("ATSR flags: %#x\n", atsr->flags); in dmar_table_print_dmar_entry()
550 (unsigned long long)rhsa->base_address, in dmar_table_print_dmar_entry()
551 rhsa->proximity_domain); in dmar_table_print_dmar_entry()
554 /* We don't print this here because we need to sanity-check in dmar_table_print_dmar_entry()
559 pr_info("SATC flags: 0x%x\n", satc->flags); in dmar_table_print_dmar_entry()
565 * dmar_table_detect - checks to see if the platform supports DMAR devices
579 return ACPI_SUCCESS(status) ? 0 : -ENOENT; in dmar_table_detect()
589 next = (void *)iter + iter->length; in dmar_walk_remapping_entries()
590 if (iter->length == 0) { in dmar_walk_remapping_entries()
592 pr_debug(FW_BUG "Invalid 0-length structure\n"); in dmar_walk_remapping_entries()
597 return -EINVAL; in dmar_walk_remapping_entries()
600 if (cb->print_entry) in dmar_walk_remapping_entries()
603 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { in dmar_walk_remapping_entries()
606 iter->type); in dmar_walk_remapping_entries()
607 } else if (cb->cb[iter->type]) { in dmar_walk_remapping_entries()
610 ret = cb->cb[iter->type](iter, cb->arg[iter->type]); in dmar_walk_remapping_entries()
613 } else if (!cb->ignore_unhandled) { in dmar_walk_remapping_entries()
614 pr_warn("No handler for DMAR structure type %d\n", in dmar_walk_remapping_entries()
615 iter->type); in dmar_walk_remapping_entries()
616 return -EINVAL; in dmar_walk_remapping_entries()
627 dmar->header.length - sizeof(*dmar), cb); in dmar_walk_dmar_table()
631 * parse_dmar_table - parses the DMA reporting table
665 return -ENODEV; in parse_dmar_table()
667 if (dmar->width < PAGE_SHIFT - 1) { in parse_dmar_table()
669 return -EINVAL; in parse_dmar_table()
672 pr_info("Host address width %d\n", dmar->width + 1); in parse_dmar_table()
675 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); in parse_dmar_table()
692 dev = dev->bus->self; in dmar_pci_device_match()
708 drhd = container_of(dmaru->hdr, in dmar_find_matched_drhd_unit()
712 if (dmaru->include_all && in dmar_find_matched_drhd_unit()
713 drhd->segment == pci_domain_nr(dev->bus)) in dmar_find_matched_drhd_unit()
716 if (dmar_pci_device_match(dmaru->devices, in dmar_find_matched_drhd_unit()
717 dmaru->devices_cnt, dev)) in dmar_find_matched_drhd_unit()
738 drhd = container_of(dmaru->hdr, in dmar_acpi_insert_dev_scope()
743 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; in dmar_acpi_insert_dev_scope()
744 scope = ((void *)scope) + scope->length) { in dmar_acpi_insert_dev_scope()
745 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) in dmar_acpi_insert_dev_scope()
747 if (scope->enumeration_id != device_number) in dmar_acpi_insert_dev_scope()
752 dev_name(&adev->dev), dmaru->reg_base_addr, in dmar_acpi_insert_dev_scope()
753 scope->bus, path->device, path->function); in dmar_acpi_insert_dev_scope()
754 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) in dmar_acpi_insert_dev_scope()
756 dmaru->devices[i].bus = scope->bus; in dmar_acpi_insert_dev_scope()
757 dmaru->devices[i].devfn = PCI_DEVFN(path->device, in dmar_acpi_insert_dev_scope()
758 path->function); in dmar_acpi_insert_dev_scope()
759 rcu_assign_pointer(dmaru->devices[i].dev, in dmar_acpi_insert_dev_scope()
760 get_device(&adev->dev)); in dmar_acpi_insert_dev_scope()
763 BUG_ON(i >= dmaru->devices_cnt); in dmar_acpi_insert_dev_scope()
766 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
767 device_number, dev_name(&adev->dev)); in dmar_acpi_insert_dev_scope()
775 return -ENODEV; in dmar_acpi_dev_scope_init()
778 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; in dmar_acpi_dev_scope_init()
779 andd = ((void *)andd) + andd->header.length) { in dmar_acpi_dev_scope_init()
780 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { in dmar_acpi_dev_scope_init()
785 andd->device_name, in dmar_acpi_dev_scope_init()
788 andd->device_name); in dmar_acpi_dev_scope_init()
794 andd->device_name); in dmar_acpi_dev_scope_init()
797 dmar_acpi_insert_dev_scope(andd->device_number, adev); in dmar_acpi_dev_scope_init()
812 dmar_dev_scope_status = -ENODEV; in dmar_dev_scope_init()
819 if (dev->is_virtfn) in dmar_dev_scope_init()
851 if (ret != -ENODEV) in dmar_table_init()
854 pr_info("No DMAR devices found\n"); in dmar_table_init()
855 ret = -ENODEV; in dmar_table_init()
887 if (!drhd->address) { in dmar_validate_one_drhd()
889 return -EINVAL; in dmar_validate_one_drhd()
893 addr = ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
895 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
897 pr_warn("Can't validate DRHD address: %llx\n", drhd->address); in dmar_validate_one_drhd()
898 return -EINVAL; in dmar_validate_one_drhd()
909 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { in dmar_validate_one_drhd()
910 warn_invalid_dmar(drhd->address, " returns all ones"); in dmar_validate_one_drhd()
911 return -EINVAL; in dmar_validate_one_drhd()
954 iounmap(iommu->reg); in unmap_iommu()
955 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
968 u64 phys_addr = drhd->reg_base_addr; in map_iommu()
971 iommu->reg_phys = phys_addr; in map_iommu()
972 iommu->reg_size = drhd->reg_size; in map_iommu()
974 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { in map_iommu()
976 err = -EBUSY; in map_iommu()
980 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
981 if (!iommu->reg) { in map_iommu()
983 err = -ENOMEM; in map_iommu()
987 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
988 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
990 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { in map_iommu()
991 err = -EINVAL; in map_iommu()
997 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), in map_iommu()
998 cap_max_fault_reg_offset(iommu->cap)); in map_iommu()
1000 if (map_size > iommu->reg_size) { in map_iommu()
1001 iounmap(iommu->reg); in map_iommu()
1002 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1003 iommu->reg_size = map_size; in map_iommu()
1004 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, in map_iommu()
1005 iommu->name)) { in map_iommu()
1007 err = -EBUSY; in map_iommu()
1010 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
1011 if (!iommu->reg) { in map_iommu()
1013 err = -ENOMEM; in map_iommu()
1018 if (cap_ecmds(iommu->cap)) { in map_iommu()
1022 iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG + in map_iommu()
1031 iounmap(iommu->reg); in map_iommu()
1033 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1042 int agaw = -1; in alloc_iommu()
1043 int msagaw = -1; in alloc_iommu()
1046 if (!drhd->reg_base_addr) { in alloc_iommu()
1048 return -EINVAL; in alloc_iommu()
1053 return -ENOMEM; in alloc_iommu()
1055 iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0, in alloc_iommu()
1056 DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL); in alloc_iommu()
1057 if (iommu->seq_id < 0) { in alloc_iommu()
1059 err = iommu->seq_id; in alloc_iommu()
1062 sprintf(iommu->name, "dmar%d", iommu->seq_id); in alloc_iommu()
1066 pr_err("Failed to map %s\n", iommu->name); in alloc_iommu()
1070 err = -EINVAL; in alloc_iommu()
1071 if (!cap_sagaw(iommu->cap) && in alloc_iommu()
1072 (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) { in alloc_iommu()
1073 pr_info("%s: No supported address widths. Not attempting DMA translation.\n", in alloc_iommu()
1074 iommu->name); in alloc_iommu()
1075 drhd->ignored = 1; in alloc_iommu()
1078 if (!drhd->ignored) { in alloc_iommu()
1082 iommu->seq_id); in alloc_iommu()
1083 drhd->ignored = 1; in alloc_iommu()
1086 if (!drhd->ignored) { in alloc_iommu()
1090 iommu->seq_id); in alloc_iommu()
1091 drhd->ignored = 1; in alloc_iommu()
1092 agaw = -1; in alloc_iommu()
1095 iommu->agaw = agaw; in alloc_iommu()
1096 iommu->msagaw = msagaw; in alloc_iommu()
1097 iommu->segment = drhd->segment; in alloc_iommu()
1099 iommu->node = NUMA_NO_NODE; in alloc_iommu()
1101 ver = readl(iommu->reg + DMAR_VER_REG); in alloc_iommu()
1103 iommu->name, in alloc_iommu()
1104 (unsigned long long)drhd->reg_base_addr, in alloc_iommu()
1106 (unsigned long long)iommu->cap, in alloc_iommu()
1107 (unsigned long long)iommu->ecap); in alloc_iommu()
1110 sts = readl(iommu->reg + DMAR_GSTS_REG); in alloc_iommu()
1112 iommu->gcmd |= DMA_GCMD_IRE; in alloc_iommu()
1114 iommu->gcmd |= DMA_GCMD_TE; in alloc_iommu()
1116 iommu->gcmd |= DMA_GCMD_QIE; in alloc_iommu()
1119 pr_debug("Cannot alloc PMU for iommu (seq_id = %d)\n", iommu->seq_id); in alloc_iommu()
1121 raw_spin_lock_init(&iommu->register_lock); in alloc_iommu()
1128 iommu->iommu.max_pasids = 2UL << ecap_pss(iommu->ecap); in alloc_iommu()
1135 if (intel_iommu_enabled && !drhd->ignored) { in alloc_iommu()
1136 err = iommu_device_sysfs_add(&iommu->iommu, NULL, in alloc_iommu()
1138 "%s", iommu->name); in alloc_iommu()
1142 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); in alloc_iommu()
1149 drhd->iommu = iommu; in alloc_iommu()
1150 iommu->drhd = drhd; in alloc_iommu()
1155 iommu_device_sysfs_remove(&iommu->iommu); in alloc_iommu()
1160 ida_free(&dmar_seq_ids, iommu->seq_id); in alloc_iommu()
1168 if (intel_iommu_enabled && !iommu->drhd->ignored) { in free_iommu()
1170 iommu_device_unregister(&iommu->iommu); in free_iommu()
1171 iommu_device_sysfs_remove(&iommu->iommu); in free_iommu()
1176 if (iommu->irq) { in free_iommu()
1177 if (iommu->pr_irq) { in free_iommu()
1178 free_irq(iommu->pr_irq, iommu); in free_iommu()
1179 dmar_free_hwirq(iommu->pr_irq); in free_iommu()
1180 iommu->pr_irq = 0; in free_iommu()
1182 free_irq(iommu->irq, iommu); in free_iommu()
1183 dmar_free_hwirq(iommu->irq); in free_iommu()
1184 iommu->irq = 0; in free_iommu()
1187 if (iommu->qi) { in free_iommu()
1188 free_page((unsigned long)iommu->qi->desc); in free_iommu()
1189 kfree(iommu->qi->desc_status); in free_iommu()
1190 kfree(iommu->qi); in free_iommu()
1193 if (iommu->reg) in free_iommu()
1196 ida_free(&dmar_seq_ids, iommu->seq_id); in free_iommu()
1205 while (qi->desc_status[qi->free_tail] == QI_FREE && qi->free_tail != qi->free_head) { in reclaim_free_desc()
1206 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; in reclaim_free_desc()
1207 qi->free_cnt++; in reclaim_free_desc()
1215 return "Context-cache Invalidation"; in qi_type_string()
1219 return "Device-TLB Invalidation"; in qi_type_string()
1225 return "PASID-based IOTLB Invalidation"; in qi_type_string()
1227 return "PASID-cache Invalidation"; in qi_type_string()
1229 return "PASID-based Device-TLB Invalidation"; in qi_type_string()
1239 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG); in qi_dump_fault()
1240 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); in qi_dump_fault()
1241 struct qi_desc *desc = iommu->qi->desc + head; in qi_dump_fault()
1244 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", in qi_dump_fault()
1247 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", in qi_dump_fault()
1250 pr_err("VT-d detected Invalidation Completion Error: SID %llx", in qi_dump_fault()
1254 qi_type_string(desc->qw0 & 0xf), in qi_dump_fault()
1255 (unsigned long long)desc->qw0, in qi_dump_fault()
1256 (unsigned long long)desc->qw1); in qi_dump_fault()
1258 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH; in qi_dump_fault()
1260 desc = iommu->qi->desc + head; in qi_dump_fault()
1263 qi_type_string(desc->qw0 & 0xf), in qi_dump_fault()
1264 (unsigned long long)desc->qw0, in qi_dump_fault()
1265 (unsigned long long)desc->qw1); in qi_dump_fault()
1272 struct q_inval *qi = iommu->qi; in qi_check_fault()
1275 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1276 return -EAGAIN; in qi_check_fault()
1278 fault = readl(iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1284 * with the error. No new descriptors are fetched until the IQE in qi_check_fault()
1288 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1290 struct qi_desc *desc = qi->desc + head; in qi_check_fault()
1293 * desc->qw2 and desc->qw3 are either reserved or in qi_check_fault()
1297 memcpy(desc, qi->desc + (wait_index << shift), in qi_check_fault()
1299 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1301 return -EINVAL; in qi_check_fault()
1307 * No new descriptors are fetched until the ITE is cleared. in qi_check_fault()
1310 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1311 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1313 tail = readl(iommu->reg + DMAR_IQT_REG); in qi_check_fault()
1314 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1316 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1317 pr_info("Invalidation Time-out Error (ITE) cleared\n"); in qi_check_fault()
1320 if (qi->desc_status[head] == QI_IN_USE) in qi_check_fault()
1321 qi->desc_status[head] = QI_ABORT; in qi_check_fault()
1322 head = (head - 2 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1325 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1326 return -EAGAIN; in qi_check_fault()
1330 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1347 struct q_inval *qi = iommu->qi; in qi_submit_sync()
1361 type = desc->qw0 & GENMASK_ULL(3, 0); in qi_submit_sync()
1378 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1384 while (qi->free_cnt < count + 2) { in qi_submit_sync()
1385 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1387 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1390 index = qi->free_head; in qi_submit_sync()
1396 memcpy(qi->desc + offset, &desc[i], 1 << shift); in qi_submit_sync()
1397 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE; in qi_submit_sync()
1401 qi->desc_status[wait_index] = QI_IN_USE; in qi_submit_sync()
1407 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); in qi_submit_sync()
1412 memcpy(qi->desc + offset, &wait_desc, 1 << shift); in qi_submit_sync()
1414 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH; in qi_submit_sync()
1415 qi->free_cnt -= count + 1; in qi_submit_sync()
1421 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); in qi_submit_sync()
1423 while (READ_ONCE(qi->desc_status[wait_index]) != QI_DONE) { in qi_submit_sync()
1435 raw_spin_unlock(&qi->q_lock); in qi_submit_sync()
1437 raw_spin_lock(&qi->q_lock); in qi_submit_sync()
1449 qi->desc_status[(index + i) % QI_LENGTH] = QI_FREE; in qi_submit_sync()
1452 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1454 if (rc == -EAGAIN) in qi_submit_sync()
1459 ktime_to_ns(ktime_get()) - iotlb_start_ktime); in qi_submit_sync()
1463 ktime_to_ns(ktime_get()) - devtlb_start_ktime); in qi_submit_sync()
1467 ktime_to_ns(ktime_get()) - iec_start_ktime); in qi_submit_sync()
1510 if (cap_write_drain(iommu->cap)) in qi_flush_iotlb()
1513 if (cap_read_drain(iommu->cap)) in qi_flush_iotlb()
1532 * VT-d spec, section 4.3: in qi_flush_dev_iotlb()
1534 * Software is recommended to not submit any Device-TLB invalidation in qi_flush_dev_iotlb()
1537 if (!(iommu->gcmd & DMA_GCMD_TE)) in qi_flush_dev_iotlb()
1541 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; in qi_flush_dev_iotlb()
1557 /* PASID-based IOTLB invalidation */
1564 * npages == -1 means a PASID-selective invalidation, otherwise, in qi_flush_piotlb()
1565 * a positive value for Page-selective-within-PASID invalidation. in qi_flush_piotlb()
1573 if (npages == -1) { in qi_flush_piotlb()
1598 /* PASID-based device IOTLB Invalidate */
1602 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); in qi_flush_dev_iotlb_pasid()
1606 * VT-d spec, section 4.3: in qi_flush_dev_iotlb_pasid()
1608 * Software is recommended to not submit any Device-TLB invalidation in qi_flush_dev_iotlb_pasid()
1611 if (!(iommu->gcmd & DMA_GCMD_TE)) in qi_flush_dev_iotlb_pasid()
1621 * range. VT-d spec 6.5.2.6. in qi_flush_dev_iotlb_pasid()
1628 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", in qi_flush_dev_iotlb_pasid()
1640 desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1, in qi_flush_dev_iotlb_pasid()
1670 if (!ecap_qis(iommu->ecap)) in dmar_disable_qi()
1673 raw_spin_lock_irqsave(&iommu->register_lock, flags); in dmar_disable_qi()
1675 sts = readl(iommu->reg + DMAR_GSTS_REG); in dmar_disable_qi()
1682 while ((readl(iommu->reg + DMAR_IQT_REG) != in dmar_disable_qi()
1683 readl(iommu->reg + DMAR_IQH_REG)) && in dmar_disable_qi()
1684 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) in dmar_disable_qi()
1687 iommu->gcmd &= ~DMA_GCMD_QIE; in dmar_disable_qi()
1688 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in dmar_disable_qi()
1693 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in dmar_disable_qi()
1703 struct q_inval *qi = iommu->qi; in __dmar_enable_qi()
1704 u64 val = virt_to_phys(qi->desc); in __dmar_enable_qi()
1706 qi->free_head = qi->free_tail = 0; in __dmar_enable_qi()
1707 qi->free_cnt = QI_LENGTH; in __dmar_enable_qi()
1713 if (ecap_smts(iommu->ecap)) in __dmar_enable_qi()
1716 raw_spin_lock_irqsave(&iommu->register_lock, flags); in __dmar_enable_qi()
1719 writel(0, iommu->reg + DMAR_IQT_REG); in __dmar_enable_qi()
1721 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
1723 iommu->gcmd |= DMA_GCMD_QIE; in __dmar_enable_qi()
1724 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in __dmar_enable_qi()
1729 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in __dmar_enable_qi()
1734 * interrupt-remapping. Also used by DMA-remapping, which replaces
1742 if (!ecap_qis(iommu->ecap)) in dmar_enable_qi()
1743 return -ENOENT; in dmar_enable_qi()
1748 if (iommu->qi) in dmar_enable_qi()
1751 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); in dmar_enable_qi()
1752 if (!iommu->qi) in dmar_enable_qi()
1753 return -ENOMEM; in dmar_enable_qi()
1755 qi = iommu->qi; in dmar_enable_qi()
1761 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, in dmar_enable_qi()
1762 !!ecap_smts(iommu->ecap)); in dmar_enable_qi()
1765 iommu->qi = NULL; in dmar_enable_qi()
1766 return -ENOMEM; in dmar_enable_qi()
1769 qi->desc = page_address(desc_page); in dmar_enable_qi()
1771 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); in dmar_enable_qi()
1772 if (!qi->desc_status) { in dmar_enable_qi()
1773 free_page((unsigned long) qi->desc); in dmar_enable_qi()
1775 iommu->qi = NULL; in dmar_enable_qi()
1776 return -ENOMEM; in dmar_enable_qi()
1779 raw_spin_lock_init(&qi->q_lock); in dmar_enable_qi()
1786 /* iommu interrupt handling. Most stuff are MSI-like. */
1806 "non-zero reserved fields in RTP",
1807 "non-zero reserved fields in CTP",
1808 "non-zero reserved fields in PTE",
1816 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1819 "SM: Non-zero reserved field set in Root Entry",
1820 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1823 "SM: Non-zero reserved field set in the Context Entry",
1828 "SM: PRE field in Context-Entry is clear",
1829 "SM: RID_PASID field error in Context-Entry",
1830 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1833 "SM: Non-zero reserved field set in PASID Directory Entry",
1834 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1837 "SM: Non-zero reserved field set in PASID Table Entry",
1838 "SM: Invalid Scalable-Mode PASID Table Entry",
1841 "Unknown", "Unknown",/* 0x5E-0x5F */
1842 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x…
1843 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x…
1844 "SM: Error attempting to access first-level paging entry",
1845 "SM: Present bit in first-level paging entry is clear",
1846 "SM: Non-zero reserved field set in first-level paging entry",
1847 "SM: Error attempting to access FL-PML4 entry",
1848 "SM: First-level entry address beyond MGAW in Nested translation",
1849 "SM: Read permission error in FL-PML4 entry in Nested translation",
1850 "SM: Read permission error in first-level paging entry in Nested translation",
1851 "SM: Write permission error in first-level paging entry in Nested translation",
1852 "SM: Error attempting to access second-level paging entry",
1853 "SM: Read/Write permission error in second-level paging entry",
1854 "SM: Non-zero reserved field set in second-level paging entry",
1855 "SM: Invalid second-level page table pointer",
1856 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1857 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1858 "SM: Address in first-level translation is not canonical",
1859 "SM: U/S set 0 for first-level translation with user privilege",
1860 "SM: No execute permission for request with PASID and ER=1",
1862 "SM: Second-level entry address beyond the max",
1863 "SM: No write permission for Write/AtomicOp request",
1864 "SM: No read permission for Read/AtomicOp request",
1865 "SM: Invalid address-interrupt address",
1866 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x…
1867 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1872 "Detected reserved fields in the decoded interrupt-remapped request",
1873 "Interrupt index exceeded the interrupt-remapping table size",
1875 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1878 "Blocked an interrupt request due to source-id verification failure",
1883 if (fault_reason >= 0x20 && (fault_reason - 0x20 < in dmar_get_fault_reason()
1886 return irq_remap_fault_reasons[fault_reason - 0x20]; in dmar_get_fault_reason()
1887 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < in dmar_get_fault_reason()
1890 return dma_remap_sm_fault_reasons[fault_reason - 0x30]; in dmar_get_fault_reason()
1903 if (iommu->irq == irq) in dmar_msi_reg()
1905 else if (iommu->pr_irq == irq) in dmar_msi_reg()
1907 else if (iommu->perf_irq == irq) in dmar_msi_reg()
1916 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_unmask()
1920 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_unmask()
1921 writel(0, iommu->reg + reg); in dmar_msi_unmask()
1923 readl(iommu->reg + reg); in dmar_msi_unmask()
1924 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_unmask()
1930 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_mask()
1934 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_mask()
1935 writel(DMA_FECTL_IM, iommu->reg + reg); in dmar_msi_mask()
1937 readl(iommu->reg + reg); in dmar_msi_mask()
1938 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_mask()
1947 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_write()
1948 writel(msg->data, iommu->reg + reg + 4); in dmar_msi_write()
1949 writel(msg->address_lo, iommu->reg + reg + 8); in dmar_msi_write()
1950 writel(msg->address_hi, iommu->reg + reg + 12); in dmar_msi_write()
1951 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_write()
1960 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_read()
1961 msg->data = readl(iommu->reg + reg + 4); in dmar_msi_read()
1962 msg->address_lo = readl(iommu->reg + reg + 8); in dmar_msi_read()
1963 msg->address_hi = readl(iommu->reg + reg + 12); in dmar_msi_read()
1964 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_read()
1977 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n", in dmar_fault_do_one()
2014 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
2015 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in dmar_fault()
2024 reg = cap_fault_reg_offset(iommu->cap); in dmar_fault()
2037 data = readl(iommu->reg + reg + in dmar_fault()
2047 data = readl(iommu->reg + reg + in dmar_fault()
2052 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
2058 writel(DMA_FRCD_F, iommu->reg + reg + in dmar_fault()
2061 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2064 /* Using pasid -1 if pasid is not present */ in dmar_fault()
2070 if (fault_index >= cap_num_fault_regs(iommu->cap)) in dmar_fault()
2072 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
2076 iommu->reg + DMAR_FSTS_REG); in dmar_fault()
2079 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2090 if (iommu->irq) in dmar_set_interrupt()
2093 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); in dmar_set_interrupt()
2095 iommu->irq = irq; in dmar_set_interrupt()
2097 pr_err("No free IRQ vectors\n"); in dmar_set_interrupt()
2098 return -EINVAL; in dmar_set_interrupt()
2101 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); in dmar_set_interrupt()
2121 (unsigned long long)drhd->reg_base_addr, ret); in enable_drhd_fault_handling()
2122 return -1; in enable_drhd_fault_handling()
2128 dmar_fault(iommu->irq, iommu); in enable_drhd_fault_handling()
2129 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2130 writel(fault_status, iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2137 * Re-enable Queued Invalidation interface.
2141 if (!ecap_qis(iommu->ecap)) in dmar_reenable_qi()
2142 return -ENOENT; in dmar_reenable_qi()
2144 if (!iommu->qi) in dmar_reenable_qi()
2145 return -ENOENT; in dmar_reenable_qi()
2152 * Then enable queued invalidation again. Since there is no pending in dmar_reenable_qi()
2153 * invalidation requests now, it's safe to re-enable queued in dmar_reenable_qi()
2170 return dmar->flags & 0x1; in dmar_ir_support()
2191 list_del(&dmaru->list); in dmar_free_unused_resources()
2204 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
2229 int ret = -ENODEV; in dmar_walk_dsm_resource()
2246 return -ENODEV; in dmar_walk_dsm_resource()
2251 start = (struct acpi_dmar_header *)obj->buffer.pointer; in dmar_walk_dsm_resource()
2252 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); in dmar_walk_dsm_resource()
2266 return -ENODEV; in dmar_hp_add_drhd()
2288 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { in dmar_hp_remove_drhd()
2289 for_each_active_dev_scope(dmaru->devices, in dmar_hp_remove_drhd()
2290 dmaru->devices_cnt, i, dev) in dmar_hp_remove_drhd()
2291 return -EBUSY; in dmar_hp_remove_drhd()
2307 list_del_rcu(&dmaru->list); in dmar_hp_release_drhd()
2328 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); in dmar_hotplug_insert()
2416 return -ENXIO; in dmar_device_hotplug()
2443 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2447 * sure no device can issue DMA outside of RMRR regions.
2460 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); in dmar_platform_optin()