Lines Matching refs:smmu
71 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
73 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
74 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
79 static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) in arm_smmu_rpm_put() argument
81 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_put()
82 pm_runtime_put_autosuspend(smmu->dev); in arm_smmu_rpm_put()
130 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
173 *smmu = dev_get_drvdata(smmu_dev); in arm_smmu_register_legacy_master()
181 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
193 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in __arm_smmu_tlb_sync() argument
199 if (smmu->impl && unlikely(smmu->impl->tlb_sync)) in __arm_smmu_tlb_sync()
200 return smmu->impl->tlb_sync(smmu, page, sync, status); in __arm_smmu_tlb_sync()
202 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in __arm_smmu_tlb_sync()
205 reg = arm_smmu_readl(smmu, page, status); in __arm_smmu_tlb_sync()
212 dev_err_ratelimited(smmu->dev, in __arm_smmu_tlb_sync()
216 static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu) in arm_smmu_tlb_sync_global() argument
220 spin_lock_irqsave(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
221 __arm_smmu_tlb_sync(smmu, ARM_SMMU_GR0, ARM_SMMU_GR0_sTLBGSYNC, in arm_smmu_tlb_sync_global()
223 spin_unlock_irqrestore(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
228 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_sync_context() local
232 __arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx), in arm_smmu_tlb_sync_context()
245 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
253 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context_s2() local
257 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_inv_context_s2()
258 arm_smmu_tlb_sync_global(smmu); in arm_smmu_tlb_inv_context_s2()
265 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s1() local
269 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s1()
276 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
283 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
293 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s2() local
296 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s2()
302 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
304 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
365 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_add_page_s2_v1() local
367 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_add_page_s2_v1()
370 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_add_page_s2_v1()
397 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_context_fault() local
401 fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); in arm_smmu_context_fault()
405 fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); in arm_smmu_context_fault()
406 iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); in arm_smmu_context_fault()
407 cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); in arm_smmu_context_fault()
413 dev_err_ratelimited(smmu->dev, in arm_smmu_context_fault()
417 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
424 struct arm_smmu_device *smmu = dev; in arm_smmu_global_fault() local
428 gfsr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
429 gfsynr0 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
430 gfsynr1 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
431 gfsynr2 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
439 dev_err(smmu->dev, in arm_smmu_global_fault()
443 dev_err(smmu->dev, in arm_smmu_global_fault()
445 dev_err(smmu->dev, in arm_smmu_global_fault()
450 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); in arm_smmu_global_fault()
458 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in arm_smmu_init_context_bank()
511 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_context_bank() argument
515 struct arm_smmu_cb *cb = &smmu->cbs[idx]; in arm_smmu_write_context_bank()
520 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
527 if (smmu->version > ARM_SMMU_V1) { in arm_smmu_write_context_bank()
533 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_write_context_bank()
536 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg); in arm_smmu_write_context_bank()
541 if (smmu->version < ARM_SMMU_V2) in arm_smmu_write_context_bank()
553 } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { in arm_smmu_write_context_bank()
557 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg); in arm_smmu_write_context_bank()
564 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()
565 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
566 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
570 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_CONTEXTIDR, cfg->asid); in arm_smmu_write_context_bank()
571 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
574 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
576 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR1, in arm_smmu_write_context_bank()
582 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR0, cb->mair[0]); in arm_smmu_write_context_bank()
583 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR1, cb->mair[1]); in arm_smmu_write_context_bank()
594 if (smmu->impl && smmu->impl->write_sctlr) in arm_smmu_write_context_bank()
595 smmu->impl->write_sctlr(smmu, idx, reg); in arm_smmu_write_context_bank()
597 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
601 struct arm_smmu_device *smmu, in arm_smmu_alloc_context_bank() argument
604 if (smmu->impl && smmu->impl->alloc_context_bank) in arm_smmu_alloc_context_bank()
605 return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_alloc_context_bank()
607 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()
611 struct arm_smmu_device *smmu, in arm_smmu_init_domain_context() argument
624 if (smmu_domain->smmu) in arm_smmu_init_domain_context()
629 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
651 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_init_domain_context()
653 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_init_domain_context()
664 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) in arm_smmu_init_domain_context()
668 (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && in arm_smmu_init_domain_context()
672 (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | in arm_smmu_init_domain_context()
685 start = smmu->num_s2_context_banks; in arm_smmu_init_domain_context()
686 ias = smmu->va_size; in arm_smmu_init_domain_context()
687 oas = smmu->ipa_size; in arm_smmu_init_domain_context()
709 ias = smmu->ipa_size; in arm_smmu_init_domain_context()
710 oas = smmu->pa_size; in arm_smmu_init_domain_context()
718 if (smmu->version == ARM_SMMU_V2) in arm_smmu_init_domain_context()
728 ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_init_domain_context()
733 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
736 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_init_domain_context()
737 cfg->irptndx = atomic_inc_return(&smmu->irptndx); in arm_smmu_init_domain_context()
738 cfg->irptndx %= smmu->num_context_irqs; in arm_smmu_init_domain_context()
749 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_init_domain_context()
752 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK, in arm_smmu_init_domain_context()
754 .iommu_dev = smmu->dev, in arm_smmu_init_domain_context()
757 if (smmu->impl && smmu->impl->init_context) { in arm_smmu_init_domain_context()
758 ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev); in arm_smmu_init_domain_context()
786 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_init_domain_context()
792 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_init_domain_context()
794 if (smmu->impl && smmu->impl->context_fault) in arm_smmu_init_domain_context()
795 context_fault = smmu->impl->context_fault; in arm_smmu_init_domain_context()
799 ret = devm_request_irq(smmu->dev, irq, context_fault, in arm_smmu_init_domain_context()
802 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", in arm_smmu_init_domain_context()
814 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_init_domain_context()
815 smmu_domain->smmu = NULL; in arm_smmu_init_domain_context()
824 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_destroy_domain_context() local
828 if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY) in arm_smmu_destroy_domain_context()
831 ret = arm_smmu_rpm_get(smmu); in arm_smmu_destroy_domain_context()
839 smmu->cbs[cfg->cbndx].cfg = NULL; in arm_smmu_destroy_domain_context()
840 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_destroy_domain_context()
843 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_destroy_domain_context()
844 devm_free_irq(smmu->dev, irq, domain); in arm_smmu_destroy_domain_context()
848 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_destroy_domain_context()
850 arm_smmu_rpm_put(smmu); in arm_smmu_destroy_domain_context()
888 static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_smr() argument
890 struct arm_smmu_smr *smr = smmu->smrs + idx; in arm_smmu_write_smr()
894 if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid) in arm_smmu_write_smr()
896 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg); in arm_smmu_write_smr()
899 static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_s2cr() argument
901 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in arm_smmu_write_s2cr()
904 if (smmu->impl && smmu->impl->write_s2cr) { in arm_smmu_write_s2cr()
905 smmu->impl->write_s2cr(smmu, idx); in arm_smmu_write_s2cr()
913 if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs && in arm_smmu_write_s2cr()
914 smmu->smrs[idx].valid) in arm_smmu_write_s2cr()
916 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in arm_smmu_write_s2cr()
919 static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_sme() argument
921 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_write_sme()
922 if (smmu->smrs) in arm_smmu_write_sme()
923 arm_smmu_write_smr(smmu, idx); in arm_smmu_write_sme()
930 static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) in arm_smmu_test_smr_masks() argument
935 if (!smmu->smrs) in arm_smmu_test_smr_masks()
945 for (i = 0; i < smmu->num_mapping_groups; i++) in arm_smmu_test_smr_masks()
946 if (!smmu->smrs[i].valid) in arm_smmu_test_smr_masks()
955 smr = FIELD_PREP(ARM_SMMU_SMR_ID, smmu->streamid_mask); in arm_smmu_test_smr_masks()
956 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
957 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
958 smmu->streamid_mask = FIELD_GET(ARM_SMMU_SMR_ID, smr); in arm_smmu_test_smr_masks()
960 smr = FIELD_PREP(ARM_SMMU_SMR_MASK, smmu->streamid_mask); in arm_smmu_test_smr_masks()
961 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
962 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
963 smmu->smr_mask_mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in arm_smmu_test_smr_masks()
966 static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) in arm_smmu_find_sme() argument
968 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_find_sme()
976 for (i = 0; i < smmu->num_mapping_groups; ++i) { in arm_smmu_find_sme()
1008 static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_free_sme() argument
1010 if (--smmu->s2crs[idx].count) in arm_smmu_free_sme()
1013 smmu->s2crs[idx] = s2cr_init_val; in arm_smmu_free_sme()
1014 if (smmu->smrs) in arm_smmu_free_sme()
1015 smmu->smrs[idx].valid = false; in arm_smmu_free_sme()
1024 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_alloc_smes() local
1025 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_master_alloc_smes()
1028 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1039 ret = arm_smmu_find_sme(smmu, sid, mask); in arm_smmu_master_alloc_smes()
1044 if (smrs && smmu->s2crs[idx].count == 0) { in arm_smmu_master_alloc_smes()
1049 smmu->s2crs[idx].count++; in arm_smmu_master_alloc_smes()
1055 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_alloc_smes()
1057 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1062 arm_smmu_free_sme(smmu, cfg->smendx[i]); in arm_smmu_master_alloc_smes()
1065 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1072 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_free_smes() local
1075 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1077 if (arm_smmu_free_sme(smmu, idx)) in arm_smmu_master_free_smes()
1078 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_free_smes()
1081 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1088 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_add_master() local
1089 struct arm_smmu_s2cr *s2cr = smmu->s2crs; in arm_smmu_domain_add_master()
1106 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_domain_add_master()
1116 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
1135 smmu = cfg->smmu; in arm_smmu_attach_dev()
1137 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev()
1142 ret = arm_smmu_init_domain_context(domain, smmu, dev); in arm_smmu_attach_dev()
1150 if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
1169 pm_runtime_set_autosuspend_delay(smmu->dev, 20); in arm_smmu_attach_dev()
1170 pm_runtime_use_autosuspend(smmu->dev); in arm_smmu_attach_dev()
1173 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev()
1182 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_map_pages() local
1188 arm_smmu_rpm_get(smmu); in arm_smmu_map_pages()
1190 arm_smmu_rpm_put(smmu); in arm_smmu_map_pages()
1200 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_unmap_pages() local
1206 arm_smmu_rpm_get(smmu); in arm_smmu_unmap_pages()
1208 arm_smmu_rpm_put(smmu); in arm_smmu_unmap_pages()
1216 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_flush_iotlb_all() local
1219 arm_smmu_rpm_get(smmu); in arm_smmu_flush_iotlb_all()
1221 arm_smmu_rpm_put(smmu); in arm_smmu_flush_iotlb_all()
1229 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iotlb_sync() local
1231 if (!smmu) in arm_smmu_iotlb_sync()
1234 arm_smmu_rpm_get(smmu); in arm_smmu_iotlb_sync()
1235 if (smmu->version == ARM_SMMU_V2 || in arm_smmu_iotlb_sync()
1239 arm_smmu_tlb_sync_global(smmu); in arm_smmu_iotlb_sync()
1240 arm_smmu_rpm_put(smmu); in arm_smmu_iotlb_sync()
1247 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iova_to_phys_hard() local
1250 struct device *dev = smmu->dev; in arm_smmu_iova_to_phys_hard()
1258 ret = arm_smmu_rpm_get(smmu); in arm_smmu_iova_to_phys_hard()
1265 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1267 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1269 reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; in arm_smmu_iova_to_phys_hard()
1276 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1280 phys = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_PAR); in arm_smmu_iova_to_phys_hard()
1290 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1304 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && in arm_smmu_iova_to_phys()
1323 return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK || in arm_smmu_capable()
1344 struct arm_smmu_device *smmu = NULL; in arm_smmu_probe_device() local
1350 ret = arm_smmu_register_legacy_master(dev, &smmu); in arm_smmu_probe_device()
1361 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
1371 if (sid & ~smmu->streamid_mask) { in arm_smmu_probe_device()
1373 sid, smmu->streamid_mask); in arm_smmu_probe_device()
1376 if (mask & ~smmu->smr_mask_mask) { in arm_smmu_probe_device()
1378 mask, smmu->smr_mask_mask); in arm_smmu_probe_device()
1389 cfg->smmu = smmu; in arm_smmu_probe_device()
1394 ret = arm_smmu_rpm_get(smmu); in arm_smmu_probe_device()
1399 arm_smmu_rpm_put(smmu); in arm_smmu_probe_device()
1404 device_link_add(dev, smmu->dev, in arm_smmu_probe_device()
1407 return &smmu->iommu; in arm_smmu_probe_device()
1422 ret = arm_smmu_rpm_get(cfg->smmu); in arm_smmu_release_device()
1428 arm_smmu_rpm_put(cfg->smmu); in arm_smmu_release_device()
1437 struct arm_smmu_device *smmu; in arm_smmu_probe_finalize() local
1440 smmu = cfg->smmu; in arm_smmu_probe_finalize()
1442 if (smmu->impl && smmu->impl->probe_finalize) in arm_smmu_probe_finalize()
1443 smmu->impl->probe_finalize(smmu, dev); in arm_smmu_probe_finalize()
1450 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_device_group() local
1454 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1456 if (group && smmu->s2crs[idx].group && in arm_smmu_device_group()
1457 group != smmu->s2crs[idx].group) { in arm_smmu_device_group()
1458 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1462 group = smmu->s2crs[idx].group; in arm_smmu_device_group()
1466 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1480 smmu->s2crs[idx].group = group; in arm_smmu_device_group()
1482 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1492 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
1508 if (smmu_domain->smmu) in arm_smmu_set_pgtable_quirks()
1551 const struct arm_smmu_impl *impl = cfg->smmu->impl; in arm_smmu_def_domain_type()
1587 static void arm_smmu_device_reset(struct arm_smmu_device *smmu) in arm_smmu_device_reset() argument
1593 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_device_reset()
1594 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); in arm_smmu_device_reset()
1600 for (i = 0; i < smmu->num_mapping_groups; ++i) in arm_smmu_device_reset()
1601 arm_smmu_write_sme(smmu, i); in arm_smmu_device_reset()
1604 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()
1605 arm_smmu_write_context_bank(smmu, i); in arm_smmu_device_reset()
1606 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); in arm_smmu_device_reset()
1610 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1611 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLNSNH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1613 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_device_reset()
1635 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_device_reset()
1638 if (smmu->features & ARM_SMMU_FEAT_EXIDS) in arm_smmu_device_reset()
1641 if (smmu->impl && smmu->impl->reset) in arm_smmu_device_reset()
1642 smmu->impl->reset(smmu); in arm_smmu_device_reset()
1645 arm_smmu_tlb_sync_global(smmu); in arm_smmu_device_reset()
1646 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_device_reset()
1668 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) in arm_smmu_device_cfg_probe() argument
1672 bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_cfg_probe()
1675 dev_notice(smmu->dev, "probing hardware configuration...\n"); in arm_smmu_device_cfg_probe()
1676 dev_notice(smmu->dev, "SMMUv%d with:\n", in arm_smmu_device_cfg_probe()
1677 smmu->version == ARM_SMMU_V2 ? 2 : 1); in arm_smmu_device_cfg_probe()
1680 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0); in arm_smmu_device_cfg_probe()
1689 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_cfg_probe()
1690 dev_notice(smmu->dev, "\tstage 1 translation\n"); in arm_smmu_device_cfg_probe()
1694 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_cfg_probe()
1695 dev_notice(smmu->dev, "\tstage 2 translation\n"); in arm_smmu_device_cfg_probe()
1699 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; in arm_smmu_device_cfg_probe()
1700 dev_notice(smmu->dev, "\tnested translation\n"); in arm_smmu_device_cfg_probe()
1703 if (!(smmu->features & in arm_smmu_device_cfg_probe()
1705 dev_err(smmu->dev, "\tno translation support!\n"); in arm_smmu_device_cfg_probe()
1710 ((smmu->version < ARM_SMMU_V2) || !(id & ARM_SMMU_ID0_ATOSNS))) { in arm_smmu_device_cfg_probe()
1711 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; in arm_smmu_device_cfg_probe()
1712 dev_notice(smmu->dev, "\taddress translation ops\n"); in arm_smmu_device_cfg_probe()
1723 dev_notice(smmu->dev, "\t%scoherent table walk\n", in arm_smmu_device_cfg_probe()
1726 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1730 if (smmu->version == ARM_SMMU_V2 && id & ARM_SMMU_ID0_EXIDS) { in arm_smmu_device_cfg_probe()
1731 smmu->features |= ARM_SMMU_FEAT_EXIDS; in arm_smmu_device_cfg_probe()
1736 smmu->streamid_mask = size - 1; in arm_smmu_device_cfg_probe()
1738 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; in arm_smmu_device_cfg_probe()
1741 dev_err(smmu->dev, in arm_smmu_device_cfg_probe()
1747 smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs), in arm_smmu_device_cfg_probe()
1749 if (!smmu->smrs) in arm_smmu_device_cfg_probe()
1752 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1756 smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs), in arm_smmu_device_cfg_probe()
1758 if (!smmu->s2crs) in arm_smmu_device_cfg_probe()
1761 smmu->s2crs[i] = s2cr_init_val; in arm_smmu_device_cfg_probe()
1763 smmu->num_mapping_groups = size; in arm_smmu_device_cfg_probe()
1764 mutex_init(&smmu->stream_map_mutex); in arm_smmu_device_cfg_probe()
1765 spin_lock_init(&smmu->global_sync_lock); in arm_smmu_device_cfg_probe()
1767 if (smmu->version < ARM_SMMU_V2 || in arm_smmu_device_cfg_probe()
1769 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L; in arm_smmu_device_cfg_probe()
1771 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S; in arm_smmu_device_cfg_probe()
1775 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID1); in arm_smmu_device_cfg_probe()
1776 smmu->pgshift = (id & ARM_SMMU_ID1_PAGESIZE) ? 16 : 12; in arm_smmu_device_cfg_probe()
1780 if (smmu->numpage != 2 * size << smmu->pgshift) in arm_smmu_device_cfg_probe()
1781 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1783 2 * size << smmu->pgshift, smmu->numpage); in arm_smmu_device_cfg_probe()
1785 smmu->numpage = size; in arm_smmu_device_cfg_probe()
1787 smmu->num_s2_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMS2CB, id); in arm_smmu_device_cfg_probe()
1788 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()
1789 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()
1790 dev_err(smmu->dev, "impossible number of S2 context banks!\n"); in arm_smmu_device_cfg_probe()
1793 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", in arm_smmu_device_cfg_probe()
1794 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()
1795 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()
1796 sizeof(*smmu->cbs), GFP_KERNEL); in arm_smmu_device_cfg_probe()
1797 if (!smmu->cbs) in arm_smmu_device_cfg_probe()
1801 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID2); in arm_smmu_device_cfg_probe()
1803 smmu->ipa_size = size; in arm_smmu_device_cfg_probe()
1807 smmu->pa_size = size; in arm_smmu_device_cfg_probe()
1810 smmu->features |= ARM_SMMU_FEAT_VMID16; in arm_smmu_device_cfg_probe()
1817 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) in arm_smmu_device_cfg_probe()
1818 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1821 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_device_cfg_probe()
1822 smmu->va_size = smmu->ipa_size; in arm_smmu_device_cfg_probe()
1823 if (smmu->version == ARM_SMMU_V1_64K) in arm_smmu_device_cfg_probe()
1824 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1827 smmu->va_size = arm_smmu_id_size_to_bits(size); in arm_smmu_device_cfg_probe()
1829 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K; in arm_smmu_device_cfg_probe()
1831 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K; in arm_smmu_device_cfg_probe()
1833 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1836 if (smmu->impl && smmu->impl->cfg_probe) { in arm_smmu_device_cfg_probe()
1837 ret = smmu->impl->cfg_probe(smmu); in arm_smmu_device_cfg_probe()
1843 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) in arm_smmu_device_cfg_probe()
1844 smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; in arm_smmu_device_cfg_probe()
1845 if (smmu->features & in arm_smmu_device_cfg_probe()
1847 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_cfg_probe()
1848 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K) in arm_smmu_device_cfg_probe()
1849 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_cfg_probe()
1850 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) in arm_smmu_device_cfg_probe()
1851 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_cfg_probe()
1854 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1856 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1857 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", in arm_smmu_device_cfg_probe()
1858 smmu->pgsize_bitmap); in arm_smmu_device_cfg_probe()
1861 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) in arm_smmu_device_cfg_probe()
1862 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", in arm_smmu_device_cfg_probe()
1863 smmu->va_size, smmu->ipa_size); in arm_smmu_device_cfg_probe()
1865 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) in arm_smmu_device_cfg_probe()
1866 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", in arm_smmu_device_cfg_probe()
1867 smmu->ipa_size, smmu->pa_size); in arm_smmu_device_cfg_probe()
1901 static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_data() argument
1908 smmu->version = ARM_SMMU_V1; in acpi_smmu_get_data()
1909 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1912 smmu->version = ARM_SMMU_V1_64K; in acpi_smmu_get_data()
1913 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1916 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1917 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1920 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1921 smmu->model = ARM_MMU500; in acpi_smmu_get_data()
1924 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1925 smmu->model = CAVIUM_SMMUV2; in acpi_smmu_get_data()
1934 static int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
1937 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
1946 ret = acpi_smmu_get_data(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
1955 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_acpi_probe()
1960 static inline int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
1967 static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, in arm_smmu_device_dt_probe() argument
1971 struct device *dev = smmu->dev; in arm_smmu_device_dt_probe()
1980 smmu->version = data->version; in arm_smmu_device_dt_probe()
1981 smmu->model = data->model; in arm_smmu_device_dt_probe()
1998 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_dt_probe()
2003 static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_smr() argument
2011 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2019 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_rmr_install_bypass_smr()
2021 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_rmr_install_bypass_smr()
2029 idx = arm_smmu_find_sme(smmu, rmr->sids[i], ~0); in arm_smmu_rmr_install_bypass_smr()
2033 if (smmu->s2crs[idx].count == 0) { in arm_smmu_rmr_install_bypass_smr()
2034 smmu->smrs[idx].id = rmr->sids[i]; in arm_smmu_rmr_install_bypass_smr()
2035 smmu->smrs[idx].mask = 0; in arm_smmu_rmr_install_bypass_smr()
2036 smmu->smrs[idx].valid = true; in arm_smmu_rmr_install_bypass_smr()
2038 smmu->s2crs[idx].count++; in arm_smmu_rmr_install_bypass_smr()
2039 smmu->s2crs[idx].type = S2CR_TYPE_BYPASS; in arm_smmu_rmr_install_bypass_smr()
2040 smmu->s2crs[idx].privcfg = S2CR_PRIVCFG_DEFAULT; in arm_smmu_rmr_install_bypass_smr()
2046 dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt, in arm_smmu_rmr_install_bypass_smr()
2048 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2054 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
2060 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
2061 if (!smmu) { in arm_smmu_device_probe()
2065 smmu->dev = dev; in arm_smmu_device_probe()
2068 err = arm_smmu_device_dt_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2070 err = arm_smmu_device_acpi_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2074 smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in arm_smmu_device_probe()
2075 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
2076 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
2077 smmu->ioaddr = res->start; in arm_smmu_device_probe()
2083 smmu->numpage = resource_size(res); in arm_smmu_device_probe()
2085 smmu = arm_smmu_impl_init(smmu); in arm_smmu_device_probe()
2086 if (IS_ERR(smmu)) in arm_smmu_device_probe()
2087 return PTR_ERR(smmu); in arm_smmu_device_probe()
2091 smmu->num_context_irqs = num_irqs - global_irqs - pmu_irqs; in arm_smmu_device_probe()
2092 if (smmu->num_context_irqs <= 0) in arm_smmu_device_probe()
2097 smmu->irqs = devm_kcalloc(dev, smmu->num_context_irqs, in arm_smmu_device_probe()
2098 sizeof(*smmu->irqs), GFP_KERNEL); in arm_smmu_device_probe()
2099 if (!smmu->irqs) in arm_smmu_device_probe()
2101 smmu->num_context_irqs); in arm_smmu_device_probe()
2103 for (i = 0; i < smmu->num_context_irqs; i++) { in arm_smmu_device_probe()
2108 smmu->irqs[i] = irq; in arm_smmu_device_probe()
2111 err = devm_clk_bulk_get_all(dev, &smmu->clks); in arm_smmu_device_probe()
2116 smmu->num_clks = err; in arm_smmu_device_probe()
2118 err = clk_bulk_prepare_enable(smmu->num_clks, smmu->clks); in arm_smmu_device_probe()
2122 err = arm_smmu_device_cfg_probe(smmu); in arm_smmu_device_probe()
2126 if (smmu->version == ARM_SMMU_V2) { in arm_smmu_device_probe()
2127 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()
2130 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()
2135 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
2138 if (smmu->impl && smmu->impl->global_fault) in arm_smmu_device_probe()
2139 global_fault = smmu->impl->global_fault; in arm_smmu_device_probe()
2150 "arm-smmu global fault", smmu); in arm_smmu_device_probe()
2157 err = iommu_device_sysfs_add(&smmu->iommu, smmu->dev, NULL, in arm_smmu_device_probe()
2158 "smmu.%pa", &smmu->ioaddr); in arm_smmu_device_probe()
2164 err = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
2167 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
2171 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
2174 arm_smmu_rmr_install_bypass_smr(smmu); in arm_smmu_device_probe()
2176 arm_smmu_device_reset(smmu); in arm_smmu_device_probe()
2177 arm_smmu_test_smr_masks(smmu); in arm_smmu_device_probe()
2195 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
2197 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) in arm_smmu_device_shutdown()
2200 arm_smmu_rpm_get(smmu); in arm_smmu_device_shutdown()
2202 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, ARM_SMMU_sCR0_CLIENTPD); in arm_smmu_device_shutdown()
2203 arm_smmu_rpm_put(smmu); in arm_smmu_device_shutdown()
2205 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_device_shutdown()
2206 pm_runtime_force_suspend(smmu->dev); in arm_smmu_device_shutdown()
2208 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2210 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2215 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
2217 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
2218 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
2225 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_resume() local
2228 ret = clk_bulk_enable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_resume()
2232 arm_smmu_device_reset(smmu); in arm_smmu_runtime_resume()
2239 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_suspend() local
2241 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_suspend()
2249 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_resume() local
2251 ret = clk_bulk_prepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2260 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2268 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_suspend() local
2278 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_suspend()