7 #include <linux/adreno-smmu-priv.h>
12 #include "arm-smmu.h"
13 #include "arm-smmu-qcom.h"
17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)  in to_qcom_smmu()  argument
19 	return container_of(smmu, struct qcom_smmu, smmu);  in to_qcom_smmu()
22 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,  in qcom_smmu_tlb_sync()  argument
28 	arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);  in qcom_smmu_tlb_sync()
31 			reg = arm_smmu_readl(smmu, page, status);  in qcom_smmu_tlb_sync()
39 	qcom_smmu_tlb_sync_debug(smmu);  in qcom_smmu_tlb_sync()
42 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,  in qcom_adreno_smmu_write_sctlr()  argument
45 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_adreno_smmu_write_sctlr()
56 	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);  in qcom_adreno_smmu_write_sctlr()
64 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_get_fault_info()  local
66 	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);  in qcom_adreno_smmu_get_fault_info()
67 	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);  in qcom_adreno_smmu_get_fault_info()
68 	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);  in qcom_adreno_smmu_get_fault_info()
69 	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);  in qcom_adreno_smmu_get_fault_info()
70 	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));  in qcom_adreno_smmu_get_fault_info()
71 	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);  in qcom_adreno_smmu_get_fault_info()
72 	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);  in qcom_adreno_smmu_get_fault_info()
79 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);  in qcom_adreno_smmu_set_stall()
91 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_resume_translation()  local
97 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);  in qcom_adreno_smmu_resume_translation()
142 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
172 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
178 					       struct arm_smmu_device *smmu,  in qcom_adreno_smmu_alloc_context_bank()  argument
192 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
195 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
198 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)  in qcom_adreno_can_do_ttbr1()  argument
200 	const struct device_node *np = smmu->dev->of_node;  in qcom_adreno_can_do_ttbr1()
202 	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))  in qcom_adreno_can_do_ttbr1()
220 	 * All targets that use the qcom,adreno-smmu compatible string *should*  in qcom_adreno_smmu_init_context()
221 	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes  in qcom_adreno_smmu_init_context()
224 	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&  in qcom_adreno_smmu_init_context()
273 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)  in qcom_smmu_cfg_probe()  argument
275 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_cfg_probe()
282 	 * MSM8998 LPASS SMMU reports 13 context banks, but accessing  in qcom_smmu_cfg_probe()
285 	if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") &&  in qcom_smmu_cfg_probe()
286 	    smmu->num_context_banks == 13) {  in qcom_smmu_cfg_probe()
287 		smmu->num_context_banks = 12;  in qcom_smmu_cfg_probe()
288 	} else if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2")) {  in qcom_smmu_cfg_probe()
289 		if (smmu->num_context_banks == 21) /* SDM630 / SDM660 A2NOC SMMU */  in qcom_smmu_cfg_probe()
290 			smmu->num_context_banks = 7;  in qcom_smmu_cfg_probe()
291 		else if (smmu->num_context_banks == 14) /* SDM630 / SDM660 LPASS SMMU */  in qcom_smmu_cfg_probe()
292 			smmu->num_context_banks = 13;  in qcom_smmu_cfg_probe()
296 	 * Some platforms support more than the Arm SMMU architected maximum of  in qcom_smmu_cfg_probe()
302 	if (smmu->num_mapping_groups > 128) {  in qcom_smmu_cfg_probe()
303 		dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");  in qcom_smmu_cfg_probe()
304 		smmu->num_mapping_groups = 128;  in qcom_smmu_cfg_probe()
307 	last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
318 	arm_smmu_gr0_write(smmu, last_s2cr, reg);  in qcom_smmu_cfg_probe()
319 	reg = arm_smmu_gr0_read(smmu, last_s2cr);  in qcom_smmu_cfg_probe()
322 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
324 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
326 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
329 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
332 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
333 		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));  in qcom_smmu_cfg_probe()
338 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
339 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
340 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
342 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
343 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
344 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
351 static int qcom_adreno_smmuv2_cfg_probe(struct arm_smmu_device *smmu)  in qcom_adreno_smmuv2_cfg_probe()  argument
354 	smmu->features &= ~ARM_SMMU_FEAT_FMT_AARCH64_16K;  in qcom_adreno_smmuv2_cfg_probe()
357 	if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm630-smmu-v2") &&  in qcom_adreno_smmuv2_cfg_probe()
358 	    smmu->num_context_banks == 5)  in qcom_adreno_smmuv2_cfg_probe()
359 		smmu->num_context_banks = 2;  in qcom_adreno_smmuv2_cfg_probe()
364 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)  in qcom_smmu_write_s2cr()  argument
366 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
367 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_write_s2cr()
396 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);  in qcom_smmu_write_s2cr()
407 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_sdm845_smmu500_reset()  argument
411 	arm_mmu500_reset(smmu);  in qcom_sdm845_smmu500_reset()
421 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
470 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,  in qcom_smmu_create()  argument
473 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_create()
480 	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))  in qcom_smmu_create()
486 		return smmu;  in qcom_smmu_create()
492 	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
496 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
499 	return &qsmmu->smmu;  in qcom_smmu_create()
514  * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
530 	 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
531 	 * by the separate sdm845-smmu-v2 device.
543  * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
544  * special handling and can not be covered by the qcom,smmu-500 entry.
547 	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
548 	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
549 	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
550 	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
551 	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
552 	{ .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
553 	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
554 	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
555 	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
556 	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
557 	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
558 	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
559 	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
560 	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
561 	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
562 	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
563 	{ .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
564 	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
565 	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
566 	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
567 	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
568 	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
569 	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
575 	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
576 	{ "QCOM  ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
581 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)  in qcom_smmu_impl_init()  argument
583 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_impl_init()
590 			return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);  in qcom_smmu_impl_init()
596 		return qcom_smmu_create(smmu, match->data);  in qcom_smmu_impl_init()
603 	WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),  in qcom_smmu_impl_init()
605 	     dev_name(smmu->dev));  in qcom_smmu_impl_init()
607 	return smmu;  in qcom_smmu_impl_init()