Lines Matching full:51
134 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
164 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
184 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
206 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
219 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
258 #define STRTAB_STE_2_S2AA64 (1UL << 51)
263 #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
277 #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
301 #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
350 #define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
377 #define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)
403 #define EVTQ_3_IPA GENMASK_ULL(51, 12)
411 #define PRIQ_0_SSID GENMASK_ULL(51, 32)