Lines Matching +full:- +full:1 +full:ul
1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define IDR0_ST_LVL_2LVL 1
28 #define IDR0_CD2L (1 << 19)
29 #define IDR0_VMID16 (1 << 18)
30 #define IDR0_PRI (1 << 16)
31 #define IDR0_SEV (1 << 14)
32 #define IDR0_MSI (1 << 13)
33 #define IDR0_ASID16 (1 << 12)
34 #define IDR0_ATS (1 << 10)
35 #define IDR0_HYP (1 << 9)
36 #define IDR0_COHACC (1 << 4)
40 #define IDR0_S1P (1 << 1)
41 #define IDR0_S2P (1 << 0)
44 #define IDR1_TABLES_PRESET (1 << 30)
45 #define IDR1_QUEUES_PRESET (1 << 29)
46 #define IDR1_REL (1 << 28)
54 #define IDR3_RIL (1 << 10)
58 #define IDR5_GRAN64K (1 << 6)
59 #define IDR5_GRAN16K (1 << 5)
60 #define IDR5_GRAN4K (1 << 4)
63 #define IDR5_OAS_36_BIT 1
70 #define IDR5_VAX_52_BIT 1
79 #define CR0_ATSCHK (1 << 4)
80 #define CR0_CMDQEN (1 << 3)
81 #define CR0_EVTQEN (1 << 2)
82 #define CR0_PRIQEN (1 << 1)
83 #define CR0_SMMUEN (1 << 0)
93 #define CR1_QUEUE_IC GENMASK(1, 0)
94 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
96 #define CR1_CACHE_WB 1
100 #define CR2_PTM (1 << 2)
101 #define CR2_RECINVSID (1 << 1)
102 #define CR2_E2H (1 << 0)
105 #define GBPA_UPDATE (1 << 31)
106 #define GBPA_ABORT (1 << 20)
109 #define IRQ_CTRL_EVTQ_IRQEN (1 << 2)
110 #define IRQ_CTRL_PRIQ_IRQEN (1 << 1)
111 #define IRQ_CTRL_GERROR_IRQEN (1 << 0)
116 #define GERROR_SFM_ERR (1 << 8)
117 #define GERROR_MSI_GERROR_ABT_ERR (1 << 7)
118 #define GERROR_MSI_PRIQ_ABT_ERR (1 << 6)
119 #define GERROR_MSI_EVTQ_ABT_ERR (1 << 5)
120 #define GERROR_MSI_CMDQ_ABT_ERR (1 << 4)
121 #define GERROR_PRIQ_ABT_ERR (1 << 3)
122 #define GERROR_EVTQ_ABT_ERR (1 << 2)
123 #define GERROR_CMDQ_ERR (1 << 0)
133 #define STRTAB_BASE_RA (1UL << 62)
139 #define STRTAB_BASE_CFG_FMT_2LVL 1
175 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
176 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
177 #define Q_OVERFLOW_FLAG (1U << 31)
179 #define Q_ENT(q, p) ((q)->base + \
180 Q_IDX(&((q)->llq), p) * \
181 (q)->ent_dwords)
183 #define Q_BASE_RWA (1UL << 62)
197 * Linear: Enough to cover 1 << IDR1.SIDSIZE entries
204 #define STRTAB_L1_DESC_DWORDS 1
209 #define STRTAB_STE_0_V (1UL << 0)
210 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
222 #define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
227 #define STRTAB_STE_1_S1C_CACHE_NC 0UL
228 #define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
229 #define STRTAB_STE_1_S1C_CACHE_WT 2UL
230 #define STRTAB_STE_1_S1C_CACHE_WB 3UL
235 #define STRTAB_STE_1_S1STALLD (1UL << 27)
238 #define STRTAB_STE_1_EATS_ABT 0UL
239 #define STRTAB_STE_1_EATS_TRANS 1UL
240 #define STRTAB_STE_1_EATS_S1CHK 2UL
243 #define STRTAB_STE_1_STRW_NSEL1 0UL
244 #define STRTAB_STE_1_STRW_EL2 2UL
247 #define STRTAB_STE_1_SHCFG_INCOMING 1UL
258 #define STRTAB_STE_2_S2AA64 (1UL << 51)
259 #define STRTAB_STE_2_S2ENDI (1UL << 52)
260 #define STRTAB_STE_2_S2PTW (1UL << 54)
261 #define STRTAB_STE_2_S2R (1UL << 58)
273 #define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT)
275 #define CTXDESC_L1_DESC_DWORDS 1
276 #define CTXDESC_L1_DESC_V (1UL << 0)
285 #define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14)
286 #define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30)
288 #define CTXDESC_CD_0_ENDI (1UL << 15)
289 #define CTXDESC_CD_0_V (1UL << 31)
292 #define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38)
294 #define CTXDESC_CD_0_AA64 (1UL << 41)
295 #define CTXDESC_CD_0_S (1UL << 44)
296 #define CTXDESC_CD_0_R (1UL << 45)
297 #define CTXDESC_CD_0_A (1UL << 46)
298 #define CTXDESC_CD_0_ASET (1UL << 47)
311 #define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3)
312 #define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
316 #define CMDQ_ERR_CERROR_ILL_IDX 1
330 #define CMDQ_0_SSV (1UL << 11)
338 #define CMDQ_CFGI_1_LEAF (1UL << 0)
346 #define CMDQ_TLBI_1_LEAF (1UL << 0)
354 #define CMDQ_ATC_0_GLOBAL (1UL << 9)
363 #define CMDQ_RESUME_0_RESP_TERM 0UL
364 #define CMDQ_RESUME_0_RESP_RETRY 1UL
365 #define CMDQ_RESUME_0_RESP_ABORT 2UL
372 #define CMDQ_SYNC_0_CS_IRQ 1
381 #define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3)
382 #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
391 #define EVTQ_0_SSV (1UL << 11)
395 #define EVTQ_1_STALL (1UL << 31)
396 #define EVTQ_1_PnU (1UL << 33)
397 #define EVTQ_1_InD (1UL << 34)
398 #define EVTQ_1_RnW (1UL << 35)
399 #define EVTQ_1_S2 (1UL << 39)
401 #define EVTQ_1_TT_READ (1UL << 44)
407 #define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3)
408 #define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
412 #define PRIQ_0_PERM_PRIV (1UL << 58)
413 #define PRIQ_0_PERM_EXEC (1UL << 59)
414 #define PRIQ_0_PERM_READ (1UL << 60)
415 #define PRIQ_0_PERM_WRITE (1UL << 61)
416 #define PRIQ_0_PRG_LAST (1UL << 62)
417 #define PRIQ_0_SSID_V (1UL << 63)
422 /* High-level queue structures */
423 #define ARM_SMMU_POLL_TIMEOUT_US 1000000 /* 1s! */
431 PRI_RESP_FAIL = 1,
440 /* Command-specific fields */
570 /* High-level stream table and context descriptor structures */
629 #define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
630 #define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
631 #define ARM_SMMU_FEAT_TT_LE (1 << 2)
632 #define ARM_SMMU_FEAT_TT_BE (1 << 3)
633 #define ARM_SMMU_FEAT_PRI (1 << 4)
634 #define ARM_SMMU_FEAT_ATS (1 << 5)
635 #define ARM_SMMU_FEAT_SEV (1 << 6)
636 #define ARM_SMMU_FEAT_MSI (1 << 7)
637 #define ARM_SMMU_FEAT_COHERENCY (1 << 8)
638 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 9)
639 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 10)
640 #define ARM_SMMU_FEAT_STALLS (1 << 11)
641 #define ARM_SMMU_FEAT_HYP (1 << 12)
642 #define ARM_SMMU_FEAT_STALL_FORCE (1 << 13)
643 #define ARM_SMMU_FEAT_VAX (1 << 14)
644 #define ARM_SMMU_FEAT_RANGE_INV (1 << 15)
645 #define ARM_SMMU_FEAT_BTM (1 << 16)
646 #define ARM_SMMU_FEAT_SVA (1 << 17)
647 #define ARM_SMMU_FEAT_E2H (1 << 18)
648 #define ARM_SMMU_FEAT_NESTING (1 << 19)
651 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
652 #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1)
653 #define ARM_SMMU_OPT_MSIPOLL (1 << 2)
654 #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3)
668 #define ARM_SMMU_MAX_ASIDS (1 << 16)
671 #define ARM_SMMU_MAX_VMIDS (1 << 16)
787 return -ENODEV; in arm_smmu_master_enable_sva()
792 return -ENODEV; in arm_smmu_master_disable_sva()