Lines Matching refs:smmu
89 static void parse_driver_options(struct arm_smmu_device *smmu) in parse_driver_options() argument
94 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
96 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
97 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
192 static void queue_poll_init(struct arm_smmu_device *smmu, in queue_poll_init() argument
197 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
348 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) in arm_smmu_get_cmdq() argument
350 return &smmu->cmdq; in arm_smmu_get_cmdq()
353 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, in arm_smmu_cmdq_build_sync_cmd() argument
364 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
372 static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_skip_err() argument
390 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
395 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
417 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
419 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
427 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) in arm_smmu_cmdq_skip_err() argument
429 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); in arm_smmu_cmdq_skip_err()
593 static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_not_full() argument
598 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in arm_smmu_cmdq_poll_until_not_full()
612 queue_poll_init(smmu, &qp); in arm_smmu_cmdq_poll_until_not_full()
628 static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_msi() argument
633 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in __arm_smmu_cmdq_poll_until_msi()
636 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_msi()
652 static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_consumed() argument
656 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in __arm_smmu_cmdq_poll_until_consumed()
660 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_consumed()
702 static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_sync() argument
705 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) in arm_smmu_cmdq_poll_until_sync()
706 return __arm_smmu_cmdq_poll_until_msi(smmu, llq); in arm_smmu_cmdq_poll_until_sync()
708 return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); in arm_smmu_cmdq_poll_until_sync()
744 static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmdlist() argument
751 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in arm_smmu_cmdq_issue_cmdlist()
765 if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) in arm_smmu_cmdq_issue_cmdlist()
766 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
791 arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); in arm_smmu_cmdq_issue_cmdlist()
841 ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); in arm_smmu_cmdq_issue_cmdlist()
843 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
864 static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_issue_cmd() argument
871 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
876 return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); in __arm_smmu_cmdq_issue_cmd()
879 static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd() argument
882 return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); in arm_smmu_cmdq_issue_cmd()
885 static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd_with_sync() argument
888 return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); in arm_smmu_cmdq_issue_cmd_with_sync()
891 static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_add() argument
898 (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) { in arm_smmu_cmdq_batch_add()
899 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); in arm_smmu_cmdq_batch_add()
904 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, false); in arm_smmu_cmdq_batch_add()
910 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in arm_smmu_cmdq_batch_add()
918 static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_submit() argument
921 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); in arm_smmu_cmdq_batch_submit()
951 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
963 void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) in arm_smmu_tlb_inv_asid() argument
966 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
971 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_asid()
981 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_sync_cd() local
996 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
1001 arm_smmu_cmdq_batch_submit(smmu, &cmds); in arm_smmu_sync_cd()
1004 static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu, in arm_smmu_alloc_cd_leaf_table() argument
1009 l1_desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_alloc_cd_leaf_table()
1012 dev_warn(smmu->dev, in arm_smmu_alloc_cd_leaf_table()
1035 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_get_cd_ptr() local
1044 if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc)) in arm_smmu_get_cd_ptr()
1140 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_alloc_cd_tables() local
1146 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1157 cdcfg->l1_desc = devm_kcalloc(smmu->dev, cdcfg->num_l1_ents, in arm_smmu_alloc_cd_tables()
1166 cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma, in arm_smmu_alloc_cd_tables()
1169 dev_warn(smmu->dev, "failed to allocate context descriptor\n"); in arm_smmu_alloc_cd_tables()
1178 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_alloc_cd_tables()
1188 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_free_cd_tables() local
1198 dmam_free_coherent(smmu->dev, size, in arm_smmu_free_cd_tables()
1202 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_free_cd_tables()
1210 dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma); in arm_smmu_free_cd_tables()
1244 static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sync_ste_for_sid() argument
1254 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_sync_ste_for_sid()
1278 struct arm_smmu_device *smmu = NULL; in arm_smmu_write_strtab_ent() local
1291 smmu = master->smmu; in arm_smmu_write_strtab_ent()
1342 if (smmu) in arm_smmu_write_strtab_ent()
1343 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1348 u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_write_strtab_ent()
1359 if (smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_write_strtab_ent()
1389 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1392 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1395 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) in arm_smmu_write_strtab_ent()
1396 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); in arm_smmu_write_strtab_ent()
1418 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_l2_strtab() argument
1422 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1432 desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma, in arm_smmu_init_l2_strtab()
1435 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1447 arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_find_master() argument
1452 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1454 node = smmu->streams.rb_node; in arm_smmu_find_master()
1469 static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_evt() argument
1540 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1541 master = arm_smmu_find_master(smmu, sid); in arm_smmu_handle_evt()
1559 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1566 struct arm_smmu_device *smmu = dev; in arm_smmu_evtq_thread() local
1567 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1577 ret = arm_smmu_handle_evt(smmu, evt); in arm_smmu_evtq_thread()
1581 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1583 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1594 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1602 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_ppr() argument
1614 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1615 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1636 arm_smmu_cmdq_issue_cmd(smmu, &cmd); in arm_smmu_handle_ppr()
1642 struct arm_smmu_device *smmu = dev; in arm_smmu_priq_thread() local
1643 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1649 arm_smmu_handle_ppr(smmu, evt); in arm_smmu_priq_thread()
1652 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1660 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
1665 struct arm_smmu_device *smmu = dev; in arm_smmu_gerror_handler() local
1667 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1668 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1674 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1679 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1680 arm_smmu_device_disable(smmu); in arm_smmu_gerror_handler()
1684 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1687 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1690 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1693 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1696 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1699 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1702 arm_smmu_cmdq_skip_err(smmu); in arm_smmu_gerror_handler()
1704 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1710 struct arm_smmu_device *smmu = dev; in arm_smmu_combined_irq_thread() local
1713 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
1803 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
1806 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
1818 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
1849 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
1854 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
1861 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context() local
1872 arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); in arm_smmu_tlb_inv_context()
1876 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_context()
1886 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range() local
1894 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1920 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1946 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
1949 arm_smmu_cmdq_batch_submit(smmu, &cmds); in __arm_smmu_tlb_inv_range()
1963 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
1984 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
2025 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_capable()
2066 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free() local
2083 ida_free(&smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free()
2095 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s1() local
2104 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2153 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s2() local
2158 vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, in arm_smmu_domain_finalise_s2()
2188 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise() local
2196 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2198 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2203 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; in arm_smmu_domain_finalise()
2205 oas = smmu->ias; in arm_smmu_domain_finalise()
2211 ias = smmu->ias; in arm_smmu_domain_finalise()
2212 oas = smmu->oas; in arm_smmu_domain_finalise()
2221 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2224 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2226 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2247 static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_get_step_for_sid() argument
2250 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2252 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2272 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev() local
2276 __le64 *step = arm_smmu_get_step_for_sid(smmu, sid); in arm_smmu_install_ste_for_dev()
2292 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported() local
2295 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2308 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats() local
2316 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2369 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2413 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
2421 smmu = master->smmu; in arm_smmu_attach_dev()
2437 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2438 smmu_domain->smmu = smmu; in arm_smmu_attach_dev()
2441 smmu_domain->smmu = NULL; in arm_smmu_attach_dev()
2444 } else if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
2511 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
2550 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sid_in_range() argument
2552 unsigned long limit = smmu->strtab_cfg.num_l1_ents; in arm_smmu_sid_in_range()
2554 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
2560 static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_sid_strtab() argument
2563 if (!arm_smmu_sid_in_range(smmu, sid)) in arm_smmu_init_sid_strtab()
2567 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_sid_strtab()
2568 return arm_smmu_init_l2_strtab(smmu, sid); in arm_smmu_init_sid_strtab()
2573 static int arm_smmu_insert_master(struct arm_smmu_device *smmu, in arm_smmu_insert_master() argument
2588 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
2596 ret = arm_smmu_init_sid_strtab(smmu, sid); in arm_smmu_insert_master()
2601 new_node = &(smmu->streams.rb_node); in arm_smmu_insert_master()
2622 rb_insert_color(&new_stream->node, &smmu->streams); in arm_smmu_insert_master()
2627 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
2630 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
2638 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master() local
2641 if (!smmu || !master->streams) in arm_smmu_remove_master()
2644 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
2646 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
2647 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
2657 struct arm_smmu_device *smmu; in arm_smmu_probe_device() local
2667 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
2668 if (!smmu) in arm_smmu_probe_device()
2676 master->smmu = smmu; in arm_smmu_probe_device()
2680 ret = arm_smmu_insert_master(smmu, master); in arm_smmu_probe_device()
2685 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
2697 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
2701 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
2703 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
2706 return &smmu->iommu; in arm_smmu_probe_device()
2719 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
2749 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
2890 static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, in arm_smmu_init_one_queue() argument
2901 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
2910 dev_err(smmu->dev, in arm_smmu_init_one_queue()
2917 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
2933 static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) in arm_smmu_cmdq_init() argument
2935 struct arm_smmu_cmdq *cmdq = &smmu->cmdq; in arm_smmu_cmdq_init()
2941 cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents, in arm_smmu_cmdq_init()
2949 static int arm_smmu_init_queues(struct arm_smmu_device *smmu) in arm_smmu_init_queues() argument
2954 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
2960 ret = arm_smmu_cmdq_init(smmu); in arm_smmu_init_queues()
2965 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
2971 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
2972 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
2973 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
2974 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
2979 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
2982 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
2987 static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_l1_strtab() argument
2990 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l1_strtab()
2991 void *strtab = smmu->strtab_cfg.strtab; in arm_smmu_init_l1_strtab()
2993 cfg->l1_desc = devm_kcalloc(smmu->dev, cfg->num_l1_ents, in arm_smmu_init_l1_strtab()
3006 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_2lvl() argument
3011 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
3015 size = min(size, smmu->sid_bits - STRTAB_SPLIT); in arm_smmu_init_strtab_2lvl()
3019 if (size < smmu->sid_bits) in arm_smmu_init_strtab_2lvl()
3020 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3022 size, smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3025 strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma, in arm_smmu_init_strtab_2lvl()
3028 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3041 return arm_smmu_init_l1_strtab(smmu); in arm_smmu_init_strtab_2lvl()
3044 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_linear() argument
3049 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3051 size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3); in arm_smmu_init_strtab_linear()
3052 strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma, in arm_smmu_init_strtab_linear()
3055 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3061 cfg->num_l1_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3065 reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_init_strtab_linear()
3072 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_strtab() argument
3077 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3078 ret = arm_smmu_init_strtab_2lvl(smmu); in arm_smmu_init_strtab()
3080 ret = arm_smmu_init_strtab_linear(smmu); in arm_smmu_init_strtab()
3086 reg = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK; in arm_smmu_init_strtab()
3088 smmu->strtab_cfg.strtab_base = reg; in arm_smmu_init_strtab()
3090 ida_init(&smmu->vmid_map); in arm_smmu_init_strtab()
3095 static int arm_smmu_init_structures(struct arm_smmu_device *smmu) in arm_smmu_init_structures() argument
3099 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3100 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3102 ret = arm_smmu_init_queues(smmu); in arm_smmu_init_structures()
3106 return arm_smmu_init_strtab(smmu); in arm_smmu_init_structures()
3109 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, in arm_smmu_write_reg_sync() argument
3114 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3115 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3120 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) in arm_smmu_update_gbpa() argument
3123 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3137 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3151 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_write_msi_msg() local
3157 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3158 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3159 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3162 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) in arm_smmu_setup_msis() argument
3165 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3168 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3169 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3171 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3172 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3176 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3180 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3191 smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); in arm_smmu_setup_msis()
3192 smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); in arm_smmu_setup_msis()
3193 smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); in arm_smmu_setup_msis()
3199 static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_unique_irqs() argument
3203 arm_smmu_setup_msis(smmu); in arm_smmu_setup_unique_irqs()
3206 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3208 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3211 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3213 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3215 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3218 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3220 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3221 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3223 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3225 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3228 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3229 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3231 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3235 smmu); in arm_smmu_setup_unique_irqs()
3237 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3240 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3245 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_irqs() argument
3251 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, in arm_smmu_setup_irqs()
3254 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3258 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3264 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3268 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3270 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3272 arm_smmu_setup_unique_irqs(smmu); in arm_smmu_setup_irqs()
3274 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3278 ret = arm_smmu_write_reg_sync(smmu, irqen_flags, in arm_smmu_setup_irqs()
3281 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3286 static int arm_smmu_device_disable(struct arm_smmu_device *smmu) in arm_smmu_device_disable() argument
3290 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); in arm_smmu_device_disable()
3292 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3297 static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) in arm_smmu_device_reset() argument
3304 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3306 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
3308 arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); in arm_smmu_device_reset()
3311 ret = arm_smmu_device_disable(smmu); in arm_smmu_device_reset()
3322 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
3327 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
3330 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
3333 writeq_relaxed(smmu->strtab_cfg.strtab_base, in arm_smmu_device_reset()
3334 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_device_reset()
3335 writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, in arm_smmu_device_reset()
3336 smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_device_reset()
3339 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3340 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
3341 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
3344 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3347 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
3353 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3356 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
3358 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3362 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3365 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3366 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
3367 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
3370 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3373 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
3378 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
3379 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
3380 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
3381 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
3382 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
3383 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
3384 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
3387 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3390 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
3395 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
3397 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3400 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
3405 ret = arm_smmu_setup_irqs(smmu); in arm_smmu_device_reset()
3407 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
3418 ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT); in arm_smmu_device_reset()
3422 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3425 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
3436 static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu) in arm_smmu_device_iidr_probe() argument
3441 reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); in arm_smmu_device_iidr_probe()
3453 smmu->features &= ~ARM_SMMU_FEAT_SEV; in arm_smmu_device_iidr_probe()
3456 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
3460 smmu->features &= ~ARM_SMMU_FEAT_BTM; in arm_smmu_device_iidr_probe()
3461 smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC; in arm_smmu_device_iidr_probe()
3463 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
3470 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) in arm_smmu_device_hw_probe() argument
3473 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
3476 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
3480 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3483 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
3492 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3496 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3500 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
3504 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
3510 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
3513 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
3516 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
3519 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
3521 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
3525 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
3527 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
3535 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
3540 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
3543 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
3547 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
3550 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
3553 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
3560 smmu->ias = 40; in arm_smmu_device_hw_probe()
3565 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
3570 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3571 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3574 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
3576 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
3581 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3583 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
3590 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
3595 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3597 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3601 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
3602 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
3603 smmu->iommu.max_pasids = 1UL << smmu->ssid_bits; in arm_smmu_device_hw_probe()
3609 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
3610 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3613 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
3615 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
3618 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
3621 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
3625 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
3627 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
3629 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
3633 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
3638 smmu->oas = 32; in arm_smmu_device_hw_probe()
3641 smmu->oas = 36; in arm_smmu_device_hw_probe()
3644 smmu->oas = 40; in arm_smmu_device_hw_probe()
3647 smmu->oas = 42; in arm_smmu_device_hw_probe()
3650 smmu->oas = 44; in arm_smmu_device_hw_probe()
3653 smmu->oas = 52; in arm_smmu_device_hw_probe()
3654 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
3657 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
3661 smmu->oas = 48; in arm_smmu_device_hw_probe()
3665 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3667 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3670 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
3671 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
3674 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
3676 if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) && in arm_smmu_device_hw_probe()
3677 (smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_device_hw_probe()
3678 smmu->features |= ARM_SMMU_FEAT_NESTING; in arm_smmu_device_hw_probe()
3680 arm_smmu_device_iidr_probe(smmu); in arm_smmu_device_hw_probe()
3682 if (arm_smmu_sva_supported(smmu)) in arm_smmu_device_hw_probe()
3683 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
3685 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
3686 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
3691 static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_options() argument
3695 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_get_options()
3698 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_get_options()
3702 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_get_options()
3706 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
3709 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
3717 acpi_smmu_get_options(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
3720 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
3726 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
3733 struct arm_smmu_device *smmu) in arm_smmu_device_dt_probe() argument
3746 parse_driver_options(smmu); in arm_smmu_device_dt_probe()
3749 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
3754 static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu) in arm_smmu_resource_size() argument
3756 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
3770 static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_ste() argument
3776 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
3785 ret = arm_smmu_init_sid_strtab(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
3787 dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n", in arm_smmu_rmr_install_bypass_ste()
3792 step = arm_smmu_get_step_for_sid(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
3797 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
3805 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
3809 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
3810 if (!smmu) in arm_smmu_device_probe()
3812 smmu->dev = dev; in arm_smmu_device_probe()
3815 ret = arm_smmu_device_dt_probe(pdev, smmu); in arm_smmu_device_probe()
3817 ret = arm_smmu_device_acpi_probe(pdev, smmu); in arm_smmu_device_probe()
3829 if (resource_size(res) < arm_smmu_resource_size(smmu)) { in arm_smmu_device_probe()
3839 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
3840 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
3841 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
3843 if (arm_smmu_resource_size(smmu) > SZ_64K) { in arm_smmu_device_probe()
3844 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
3846 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
3847 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
3849 smmu->page1 = smmu->base; in arm_smmu_device_probe()
3856 smmu->combined_irq = irq; in arm_smmu_device_probe()
3860 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
3864 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
3868 smmu->gerr_irq = irq; in arm_smmu_device_probe()
3871 ret = arm_smmu_device_hw_probe(smmu); in arm_smmu_device_probe()
3876 ret = arm_smmu_init_structures(smmu); in arm_smmu_device_probe()
3881 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
3884 arm_smmu_rmr_install_bypass_ste(smmu); in arm_smmu_device_probe()
3887 ret = arm_smmu_device_reset(smmu, bypass); in arm_smmu_device_probe()
3892 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
3897 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
3900 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
3909 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
3911 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
3912 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
3913 arm_smmu_device_disable(smmu); in arm_smmu_device_remove()
3914 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
3915 ida_destroy(&smmu->vmid_map); in arm_smmu_device_remove()
3920 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
3922 arm_smmu_device_disable(smmu); in arm_smmu_device_shutdown()