Lines Matching refs:cmd
247 static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) in arm_smmu_cmdq_build_cmd() argument
249 memset(cmd, 0, 1 << CMDQ_ENT_SZ_SHIFT); in arm_smmu_cmdq_build_cmd()
250 cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode); in arm_smmu_cmdq_build_cmd()
257 cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid); in arm_smmu_cmdq_build_cmd()
260 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid); in arm_smmu_cmdq_build_cmd()
263 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
264 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf); in arm_smmu_cmdq_build_cmd()
267 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
271 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); in arm_smmu_cmdq_build_cmd()
274 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
277 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
278 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
279 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
280 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
281 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
282 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
283 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK; in arm_smmu_cmdq_build_cmd()
286 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
287 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
288 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
289 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
290 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
291 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
292 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK; in arm_smmu_cmdq_build_cmd()
295 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
298 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
301 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
304 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
305 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global); in arm_smmu_cmdq_build_cmd()
306 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid); in arm_smmu_cmdq_build_cmd()
307 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid); in arm_smmu_cmdq_build_cmd()
308 cmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size); in arm_smmu_cmdq_build_cmd()
309 cmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK; in arm_smmu_cmdq_build_cmd()
312 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
313 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid); in arm_smmu_cmdq_build_cmd()
314 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid); in arm_smmu_cmdq_build_cmd()
315 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid); in arm_smmu_cmdq_build_cmd()
324 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp); in arm_smmu_cmdq_build_cmd()
327 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_SID, ent->resume.sid); in arm_smmu_cmdq_build_cmd()
328 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); in arm_smmu_cmdq_build_cmd()
329 cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); in arm_smmu_cmdq_build_cmd()
333 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); in arm_smmu_cmdq_build_cmd()
334 cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; in arm_smmu_cmdq_build_cmd()
336 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); in arm_smmu_cmdq_build_cmd()
338 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); in arm_smmu_cmdq_build_cmd()
339 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); in arm_smmu_cmdq_build_cmd()
353 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, in arm_smmu_cmdq_build_sync_cmd() argument
369 arm_smmu_cmdq_build_cmd(cmd, &ent); in arm_smmu_cmdq_build_sync_cmd()
383 u64 cmd[CMDQ_ENT_DWORDS]; in __arm_smmu_cmdq_skip_err() local
416 queue_read(cmd, Q_ENT(q, cons), q->ent_dwords); in __arm_smmu_cmdq_skip_err()
418 for (i = 0; i < ARRAY_SIZE(cmd); ++i) in __arm_smmu_cmdq_skip_err()
419 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
422 arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); in __arm_smmu_cmdq_skip_err()
424 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); in __arm_smmu_cmdq_skip_err()
634 u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); in __arm_smmu_cmdq_poll_until_msi() local
643 smp_cond_load_relaxed(cmd, !VAL || (ret = queue_poll(&qp))); in __arm_smmu_cmdq_poll_until_msi()
721 u64 *cmd = &cmds[i * CMDQ_ENT_DWORDS]; in arm_smmu_cmdq_write_entries() local
724 queue_write(Q_ENT(&cmdq->q, prod), cmd, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_write_entries()
868 u64 cmd[CMDQ_ENT_DWORDS]; in __arm_smmu_cmdq_issue_cmd() local
870 if (unlikely(arm_smmu_cmdq_build_cmd(cmd, ent))) { in __arm_smmu_cmdq_issue_cmd()
876 return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); in __arm_smmu_cmdq_issue_cmd()
893 struct arm_smmu_cmdq_ent *cmd) in arm_smmu_cmdq_batch_add() argument
909 if (unlikely(arm_smmu_cmdq_build_cmd(&cmds->cmds[index], cmd))) { in arm_smmu_cmdq_batch_add()
911 cmd->opcode); in arm_smmu_cmdq_batch_add()
928 struct arm_smmu_cmdq_ent cmd = {0}; in arm_smmu_page_response() local
933 cmd.opcode = CMDQ_OP_RESUME; in arm_smmu_page_response()
934 cmd.resume.sid = sid; in arm_smmu_page_response()
935 cmd.resume.stag = resp->grpid; in arm_smmu_page_response()
939 cmd.resume.resp = CMDQ_RESUME_0_RESP_ABORT; in arm_smmu_page_response()
942 cmd.resume.resp = CMDQ_RESUME_0_RESP_RETRY; in arm_smmu_page_response()
951 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
965 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_tlb_inv_asid() local
971 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_asid()
982 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_sync_cd() local
995 cmd.cfgi.sid = master->streams[i].id; in arm_smmu_sync_cd()
996 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
1246 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_sync_ste_for_sid() local
1254 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_sync_ste_for_sid()
1625 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_handle_ppr() local
1636 arm_smmu_cmdq_issue_cmd(smmu, &cmd); in arm_smmu_handle_ppr()
1727 struct arm_smmu_cmdq_ent *cmd) in arm_smmu_atc_inv_to_cmd() argument
1749 *cmd = (struct arm_smmu_cmdq_ent) { in arm_smmu_atc_inv_to_cmd()
1756 cmd->atc.size = ATC_INV_SIZE_ALL; in arm_smmu_atc_inv_to_cmd()
1788 cmd->atc.addr = page_start << inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
1789 cmd->atc.size = log2_span; in arm_smmu_atc_inv_to_cmd()
1795 struct arm_smmu_cmdq_ent cmd; in arm_smmu_atc_inv_master() local
1798 arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); in arm_smmu_atc_inv_master()
1802 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_master()
1803 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
1814 struct arm_smmu_cmdq_ent cmd; in arm_smmu_atc_inv_domain() local
1838 arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd); in arm_smmu_atc_inv_domain()
1848 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_domain()
1849 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
1862 struct arm_smmu_cmdq_ent cmd; in arm_smmu_tlb_inv_context() local
1874 cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; in arm_smmu_tlb_inv_context()
1875 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_context()
1876 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_context()
1881 static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, in __arm_smmu_tlb_inv_range() argument
1901 cmd->tlbi.tg = (tg - 10) / 2; in __arm_smmu_tlb_inv_range()
1911 if (cmd->tlbi.leaf) in __arm_smmu_tlb_inv_range()
1912 cmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); in __arm_smmu_tlb_inv_range()
1932 cmd->tlbi.scale = scale; in __arm_smmu_tlb_inv_range()
1936 cmd->tlbi.num = num - 1; in __arm_smmu_tlb_inv_range()
1945 cmd->tlbi.addr = iova; in __arm_smmu_tlb_inv_range()
1946 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
1956 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_tlb_inv_range_domain() local
1963 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
1965 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; in arm_smmu_tlb_inv_range_domain()
1967 cmd.opcode = CMDQ_OP_TLBI_S2_IPA; in arm_smmu_tlb_inv_range_domain()
1968 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_range_domain()
1970 __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); in arm_smmu_tlb_inv_range_domain()
1983 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_tlb_inv_range_asid() local
1992 __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); in arm_smmu_tlb_inv_range_asid()
3301 struct arm_smmu_cmdq_ent cmd; in arm_smmu_device_reset() local
3352 cmd.opcode = CMDQ_OP_CFGI_ALL; in arm_smmu_device_reset()
3353 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3357 cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; in arm_smmu_device_reset()
3358 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3361 cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; in arm_smmu_device_reset()
3362 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()