111 	u32 efr_attr;
127 		u32 ext;
128 		u32 hidh;
190 u32 amd_iommu_max_pasid __read_mostly = ~0;
237 static u32 amd_iommu_ivinfo __initdata;
335 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)  in iommu_read_l1()
337 	u32 val;  in iommu_read_l1()
344 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)  in iommu_write_l1()
351 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)  in iommu_read_l2()
353 	u32 val;  in iommu_read_l2()
360 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)  in iommu_write_l2()
424 	u32 dev_table_size = iommu->pci_seg->dev_table_size;  in iommu_set_device_table()
520 static inline u32 get_ivhd_header_size(struct ivhd_header *h)  in get_ivhd_header_size()
522 	u32 size = 0;  in get_ivhd_header_size()
550 	u32 type = ((struct ivhd_entry *)ivhd)->type;  in ivhd_entry_length()
571 	u32 ivhd_size = get_ivhd_header_size(h);  in find_last_devid_from_ivhd()
765 				  u32 status_run_mask, u32 status_overflow_mask)  in amd_iommu_restart_log()
767 	u32 status;  in amd_iommu_restart_log()
968 	u32 status, i;  in iommu_ga_log_enable()
1095 	u32 lo, hi, devid, old_devtb_size;  in __copy_device_table()
1223 					   u16 devid, u32 flags, u32 ext_flags)  in set_dev_entry_from_acpi()
1245 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line)  in add_special_device()
1282 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u32 *devid,  in add_acpi_hid_device()
1362 	u32 dev_i, ext_flags = 0;  in init_iommu_from_acpi()
1366 	u32 ivhd_size;  in init_iommu_from_acpi()
1518 			u32 devid;  in init_iommu_from_acpi()
1552 			u32 devid;  in init_iommu_from_acpi()
1733 	u32 value;  in amd_iommu_erratum_746_workaround()
1764 	u32 value;  in amd_iommu_ats_write_check_workaround()
2109 		u32 max_pasid;  in iommu_init_pci()
2655 	u32 devid;  in init_device_table_dma()
2670 	u32 devid;  in uninit_device_table_dma()
2685 	u32 devid;  in init_device_table()
2727 	u32 ioc_feature_control;  in iommu_apply_resume_quirks()
2896 	u32 status, i;  in enable_iommus_vapic()
3076 	amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET));  in ivinfo_init()
3180 			remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);  in early_amd_iommu_init()
3254 		u32 pci_id;  in detect_ivrs()
3548 	u32 seg = 0, bus, dev, fn;  in parse_ivrs_ioapic()
3550 	u32 devid;  in parse_ivrs_ioapic()
3586 	u32 seg = 0, bus, dev, fn;  in parse_ivrs_hpet()
3588 	u32 devid;  in parse_ivrs_hpet()
3626 	u32 seg = 0, bus, dev, fn;  in parse_ivrs_acpihid()
3766 	u32 offset;  in iommu_pc_get_set_reg()
3767 	u32 max_offset_lim;  in iommu_pc_get_set_reg()
3777 	offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);  in iommu_pc_get_set_reg()
3780 	max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |  in iommu_pc_get_set_reg()
3789 		writel((u32)val, iommu->mmio_base + offset);  in iommu_pc_get_set_reg()