Lines Matching full:x1
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
53 #define QIB_6120_Control_TxLatency_RMASK 0x1
55 #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1
57 #define QIB_6120_Control_LinkEn_RMASK 0x1
58 #define QIB_6120_Control_FreezeMode_LSB 0x1
59 #define QIB_6120_Control_FreezeMode_RMASK 0x1
61 #define QIB_6120_Control_SyncReset_RMASK 0x1
81 #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1
83 #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1
85 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1
87 #define QIB_6120_IntBlocked_assertGPIOIntBlocked_RMASK 0x1
91 #define QIB_6120_IntBlocked_RcvAvail4IntBlocked_RMASK 0x1
93 #define QIB_6120_IntBlocked_RcvAvail3IntBlocked_RMASK 0x1
95 #define QIB_6120_IntBlocked_RcvAvail2IntBlocked_RMASK 0x1
97 #define QIB_6120_IntBlocked_RcvAvail1IntBlocked_RMASK 0x1
99 #define QIB_6120_IntBlocked_RcvAvail0IntBlocked_RMASK 0x1
103 #define QIB_6120_IntBlocked_RcvUrg4IntBlocked_RMASK 0x1
105 #define QIB_6120_IntBlocked_RcvUrg3IntBlocked_RMASK 0x1
107 #define QIB_6120_IntBlocked_RcvUrg2IntBlocked_RMASK 0x1
108 #define QIB_6120_IntBlocked_RcvUrg1IntBlocked_LSB 0x1
109 #define QIB_6120_IntBlocked_RcvUrg1IntBlocked_RMASK 0x1
111 #define QIB_6120_IntBlocked_RcvUrg0IntBlocked_RMASK 0x1
115 #define QIB_6120_IntMask_ErrorIntMask_RMASK 0x1
117 #define QIB_6120_IntMask_PioSetIntMask_RMASK 0x1
119 #define QIB_6120_IntMask_PioBufAvailIntMask_RMASK 0x1
121 #define QIB_6120_IntMask_assertGPIOIntMask_RMASK 0x1
125 #define QIB_6120_IntMask_RcvAvail4IntMask_RMASK 0x1
127 #define QIB_6120_IntMask_RcvAvail3IntMask_RMASK 0x1
129 #define QIB_6120_IntMask_RcvAvail2IntMask_RMASK 0x1
131 #define QIB_6120_IntMask_RcvAvail1IntMask_RMASK 0x1
133 #define QIB_6120_IntMask_RcvAvail0IntMask_RMASK 0x1
137 #define QIB_6120_IntMask_RcvUrg4IntMask_RMASK 0x1
139 #define QIB_6120_IntMask_RcvUrg3IntMask_RMASK 0x1
141 #define QIB_6120_IntMask_RcvUrg2IntMask_RMASK 0x1
142 #define QIB_6120_IntMask_RcvUrg1IntMask_LSB 0x1
143 #define QIB_6120_IntMask_RcvUrg1IntMask_RMASK 0x1
145 #define QIB_6120_IntMask_RcvUrg0IntMask_RMASK 0x1
149 #define QIB_6120_IntStatus_Error_RMASK 0x1
151 #define QIB_6120_IntStatus_PioSent_RMASK 0x1
153 #define QIB_6120_IntStatus_PioBufAvail_RMASK 0x1
155 #define QIB_6120_IntStatus_assertGPIO_RMASK 0x1
159 #define QIB_6120_IntStatus_RcvAvail4_RMASK 0x1
161 #define QIB_6120_IntStatus_RcvAvail3_RMASK 0x1
163 #define QIB_6120_IntStatus_RcvAvail2_RMASK 0x1
165 #define QIB_6120_IntStatus_RcvAvail1_RMASK 0x1
167 #define QIB_6120_IntStatus_RcvAvail0_RMASK 0x1
171 #define QIB_6120_IntStatus_RcvUrg4_RMASK 0x1
173 #define QIB_6120_IntStatus_RcvUrg3_RMASK 0x1
175 #define QIB_6120_IntStatus_RcvUrg2_RMASK 0x1
176 #define QIB_6120_IntStatus_RcvUrg1_LSB 0x1
177 #define QIB_6120_IntStatus_RcvUrg1_RMASK 0x1
179 #define QIB_6120_IntStatus_RcvUrg0_RMASK 0x1
183 #define QIB_6120_IntClear_ErrorIntClear_RMASK 0x1
185 #define QIB_6120_IntClear_PioSetIntClear_RMASK 0x1
187 #define QIB_6120_IntClear_PioBufAvailIntClear_RMASK 0x1
189 #define QIB_6120_IntClear_assertGPIOIntClear_RMASK 0x1
193 #define QIB_6120_IntClear_RcvAvail4IntClear_RMASK 0x1
195 #define QIB_6120_IntClear_RcvAvail3IntClear_RMASK 0x1
197 #define QIB_6120_IntClear_RcvAvail2IntClear_RMASK 0x1
199 #define QIB_6120_IntClear_RcvAvail1IntClear_RMASK 0x1
201 #define QIB_6120_IntClear_RcvAvail0IntClear_RMASK 0x1
205 #define QIB_6120_IntClear_RcvUrg4IntClear_RMASK 0x1
207 #define QIB_6120_IntClear_RcvUrg3IntClear_RMASK 0x1
209 #define QIB_6120_IntClear_RcvUrg2IntClear_RMASK 0x1
210 #define QIB_6120_IntClear_RcvUrg1IntClear_LSB 0x1
211 #define QIB_6120_IntClear_RcvUrg1IntClear_RMASK 0x1
213 #define QIB_6120_IntClear_RcvUrg0IntClear_RMASK 0x1
219 #define QIB_6120_ErrMask_HardwareErrMask_RMASK 0x1
221 #define QIB_6120_ErrMask_ResetNegatedMask_RMASK 0x1
223 #define QIB_6120_ErrMask_InvalidAddrErrMask_RMASK 0x1
225 #define QIB_6120_ErrMask_IBStatusChangedMask_RMASK 0x1
229 #define QIB_6120_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1
231 #define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1
233 #define QIB_6120_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1
235 #define QIB_6120_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1
237 #define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1
239 #define QIB_6120_ErrMask_SendPktLenErrMask_RMASK 0x1
241 #define QIB_6120_ErrMask_SendUnderRunErrMask_RMASK 0x1
243 #define QIB_6120_ErrMask_SendMaxPktLenErrMask_RMASK 0x1
245 #define QIB_6120_ErrMask_SendMinPktLenErrMask_RMASK 0x1
249 #define QIB_6120_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1
251 #define QIB_6120_ErrMask_RcvHdrErrMask_RMASK 0x1
253 #define QIB_6120_ErrMask_RcvHdrLenErrMask_RMASK 0x1
255 #define QIB_6120_ErrMask_RcvBadTidErrMask_RMASK 0x1
257 #define QIB_6120_ErrMask_RcvHdrFullErrMask_RMASK 0x1
259 #define QIB_6120_ErrMask_RcvEgrFullErrMask_RMASK 0x1
261 #define QIB_6120_ErrMask_RcvBadVersionErrMask_RMASK 0x1
263 #define QIB_6120_ErrMask_RcvIBFlowErrMask_RMASK 0x1
265 #define QIB_6120_ErrMask_RcvEBPErrMask_RMASK 0x1
267 #define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1
269 #define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1
271 #define QIB_6120_ErrMask_RcvShortPktLenErrMask_RMASK 0x1
273 #define QIB_6120_ErrMask_RcvLongPktLenErrMask_RMASK 0x1
275 #define QIB_6120_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1
277 #define QIB_6120_ErrMask_RcvMinPktLenErrMask_RMASK 0x1
279 #define QIB_6120_ErrMask_RcvICRCErrMask_RMASK 0x1
280 #define QIB_6120_ErrMask_RcvVCRCErrMask_LSB 0x1
281 #define QIB_6120_ErrMask_RcvVCRCErrMask_RMASK 0x1
283 #define QIB_6120_ErrMask_RcvFormatErrMask_RMASK 0x1
289 #define QIB_6120_ErrStatus_HardwareErr_RMASK 0x1
291 #define QIB_6120_ErrStatus_ResetNegated_RMASK 0x1
293 #define QIB_6120_ErrStatus_InvalidAddrErr_RMASK 0x1
295 #define QIB_6120_ErrStatus_IBStatusChanged_RMASK 0x1
299 #define QIB_6120_ErrStatus_SendUnsupportedVLErr_RMASK 0x1
301 #define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1
303 #define QIB_6120_ErrStatus_SendPioArmLaunchErr_RMASK 0x1
305 #define QIB_6120_ErrStatus_SendDroppedDataPktErr_RMASK 0x1
307 #define QIB_6120_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1
309 #define QIB_6120_ErrStatus_SendPktLenErr_RMASK 0x1
311 #define QIB_6120_ErrStatus_SendUnderRunErr_RMASK 0x1
313 #define QIB_6120_ErrStatus_SendMaxPktLenErr_RMASK 0x1
315 #define QIB_6120_ErrStatus_SendMinPktLenErr_RMASK 0x1
319 #define QIB_6120_ErrStatus_RcvIBLostLinkErr_RMASK 0x1
321 #define QIB_6120_ErrStatus_RcvHdrErr_RMASK 0x1
323 #define QIB_6120_ErrStatus_RcvHdrLenErr_RMASK 0x1
325 #define QIB_6120_ErrStatus_RcvBadTidErr_RMASK 0x1
327 #define QIB_6120_ErrStatus_RcvHdrFullErr_RMASK 0x1
329 #define QIB_6120_ErrStatus_RcvEgrFullErr_RMASK 0x1
331 #define QIB_6120_ErrStatus_RcvBadVersionErr_RMASK 0x1
333 #define QIB_6120_ErrStatus_RcvIBFlowErr_RMASK 0x1
335 #define QIB_6120_ErrStatus_RcvEBPErr_RMASK 0x1
337 #define QIB_6120_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1
339 #define QIB_6120_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1
341 #define QIB_6120_ErrStatus_RcvShortPktLenErr_RMASK 0x1
343 #define QIB_6120_ErrStatus_RcvLongPktLenErr_RMASK 0x1
345 #define QIB_6120_ErrStatus_RcvMaxPktLenErr_RMASK 0x1
347 #define QIB_6120_ErrStatus_RcvMinPktLenErr_RMASK 0x1
349 #define QIB_6120_ErrStatus_RcvICRCErr_RMASK 0x1
350 #define QIB_6120_ErrStatus_RcvVCRCErr_LSB 0x1
351 #define QIB_6120_ErrStatus_RcvVCRCErr_RMASK 0x1
353 #define QIB_6120_ErrStatus_RcvFormatErr_RMASK 0x1
359 #define QIB_6120_ErrClear_HardwareErrClear_RMASK 0x1
361 #define QIB_6120_ErrClear_ResetNegatedClear_RMASK 0x1
363 #define QIB_6120_ErrClear_InvalidAddrErrClear_RMASK 0x1
365 #define QIB_6120_ErrClear_IBStatusChangedClear_RMASK 0x1
369 #define QIB_6120_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1
371 #define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1
373 #define QIB_6120_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1
375 #define QIB_6120_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1
377 #define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1
379 #define QIB_6120_ErrClear_SendPktLenErrClear_RMASK 0x1
381 #define QIB_6120_ErrClear_SendUnderRunErrClear_RMASK 0x1
383 #define QIB_6120_ErrClear_SendMaxPktLenErrClear_RMASK 0x1
385 #define QIB_6120_ErrClear_SendMinPktLenErrClear_RMASK 0x1
389 #define QIB_6120_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1
391 #define QIB_6120_ErrClear_RcvHdrErrClear_RMASK 0x1
393 #define QIB_6120_ErrClear_RcvHdrLenErrClear_RMASK 0x1
395 #define QIB_6120_ErrClear_RcvBadTidErrClear_RMASK 0x1
397 #define QIB_6120_ErrClear_RcvHdrFullErrClear_RMASK 0x1
399 #define QIB_6120_ErrClear_RcvEgrFullErrClear_RMASK 0x1
401 #define QIB_6120_ErrClear_RcvBadVersionErrClear_RMASK 0x1
403 #define QIB_6120_ErrClear_RcvIBFlowErrClear_RMASK 0x1
405 #define QIB_6120_ErrClear_RcvEBPErrClear_RMASK 0x1
407 #define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1
409 #define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1
411 #define QIB_6120_ErrClear_RcvShortPktLenErrClear_RMASK 0x1
413 #define QIB_6120_ErrClear_RcvLongPktLenErrClear_RMASK 0x1
415 #define QIB_6120_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1
417 #define QIB_6120_ErrClear_RcvMinPktLenErrClear_RMASK 0x1
419 #define QIB_6120_ErrClear_RcvICRCErrClear_RMASK 0x1
420 #define QIB_6120_ErrClear_RcvVCRCErrClear_LSB 0x1
421 #define QIB_6120_ErrClear_RcvVCRCErrClear_RMASK 0x1
423 #define QIB_6120_ErrClear_RcvFormatErrClear_RMASK 0x1
427 #define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1
429 #define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1
431 #define QIB_6120_HwErrMask_Reserved_RMASK 0x1
433 #define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1
435 #define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1
437 #define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1
439 #define QIB_6120_HwErrMask_Reserved1_RMASK 0x1
441 #define QIB_6120_HwErrMask_IBPLLrfSlipMask_RMASK 0x1
443 #define QIB_6120_HwErrMask_IBPLLfbSlipMask_RMASK 0x1
445 #define QIB_6120_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1
457 #define QIB_6120_HwErrMask_PcieCplTimeoutMask_RMASK 0x1
459 #define QIB_6120_HwErrMask_PoisonedTLPMask_RMASK 0x1
467 #define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1
469 #define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1
471 #define QIB_6120_HwErrStatus_Reserved_RMASK 0x1
473 #define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1
475 #define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1
477 #define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1
479 #define QIB_6120_HwErrStatus_Reserved1_RMASK 0x1
481 #define QIB_6120_HwErrStatus_IBPLLrfSlip_RMASK 0x1
483 #define QIB_6120_HwErrStatus_IBPLLfbSlip_RMASK 0x1
485 #define QIB_6120_HwErrStatus_PowerOnBISTFailed_RMASK 0x1
497 #define QIB_6120_HwErrStatus_PcieCplTimeout_RMASK 0x1
499 #define QIB_6120_HwErrStatus_PoisenedTLP_RMASK 0x1
507 #define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1
509 #define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1
511 #define QIB_6120_HwErrClear_Reserved_RMASK 0x1
513 #define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1
515 #define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1
517 #define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1
519 #define QIB_6120_HwErrClear_Reserved1_RMASK 0x1
521 #define QIB_6120_HwErrClear_IBPLLrfSlipClear_RMASK 0x1
523 #define QIB_6120_HwErrClear_IBPLLfbSlipClear_RMASK 0x1
525 #define QIB_6120_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1
537 #define QIB_6120_HwErrClear_PcieCplTimeoutClear_RMASK 0x1
539 #define QIB_6120_HwErrClear_PoisonedTLPClear_RMASK 0x1
547 #define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1
549 #define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1
551 #define QIB_6120_HwDiagCtrl_CounterWrEnable_RMASK 0x1
553 #define QIB_6120_HwDiagCtrl_CounterDisable_RMASK 0x1
571 #define QIB_6120_IBCStatus_TxCreditOk_RMASK 0x1
573 #define QIB_6120_IBCStatus_TxReady_RMASK 0x1
583 #define QIB_6120_IBCCtrl_Loopback_RMASK 0x1
585 #define QIB_6120_IBCCtrl_LinkDownDefaultState_RMASK 0x1
595 #define QIB_6120_IBCCtrl_Reserved1_RMASK 0x1
615 #define QIB_6120_EXTStatus_MemBISTFoundErr_RMASK 0x1
617 #define QIB_6120_EXTStatus_MemBISTEndTest_RMASK 0x1
629 #define QIB_6120_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1
631 #define QIB_6120_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1
632 #define QIB_6120_EXTCtrl_LEDGblOkGreenOn_LSB 0x1
633 #define QIB_6120_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1
635 #define QIB_6120_EXTCtrl_LEDGblErrRedOff_RMASK 0x1
647 #define QIB_6120_RcvCtrl_TailUpd_RMASK 0x1
649 #define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1
701 #define QIB_6120_SendCtrl_Disarm_RMASK 0x1
709 #define QIB_6120_SendCtrl_PIOEnable_RMASK 0x1
711 #define QIB_6120_SendCtrl_PIOBufAvailUpd_RMASK 0x1
712 #define QIB_6120_SendCtrl_PIOIntBufAvail_LSB 0x1
713 #define QIB_6120_SendCtrl_PIOIntBufAvail_RMASK 0x1
715 #define QIB_6120_SendCtrl_Abort_RMASK 0x1
771 #define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_RMASK 0x1
781 #define QIB_6120_SerdesCfg0_TermAdj1_RMASK 0x1
783 #define QIB_6120_SerdesCfg0_TermAdj0_RMASK 0x1
785 #define QIB_6120_SerdesCfg0_LPBKA_RMASK 0x1
787 #define QIB_6120_SerdesCfg0_LPBKB_RMASK 0x1
789 #define QIB_6120_SerdesCfg0_LPBKC_RMASK 0x1
791 #define QIB_6120_SerdesCfg0_LPBKD_RMASK 0x1
793 #define QIB_6120_SerdesCfg0_PW_RMASK 0x1
797 #define QIB_6120_SerdesCfg0_ParReset_RMASK 0x1
799 #define QIB_6120_SerdesCfg0_ParLPBK_RMASK 0x1
801 #define QIB_6120_SerdesCfg0_OffsetEn_RMASK 0x1
805 #define QIB_6120_SerdesCfg0_L2PwrDn_RMASK 0x1
807 #define QIB_6120_SerdesCfg0_ResetPLL_RMASK 0x1
819 #define QIB_6120_SerdesCfg0_L1PwrDnA_RMASK 0x1
821 #define QIB_6120_SerdesCfg0_L1PwrDnB_RMASK 0x1
823 #define QIB_6120_SerdesCfg0_L1PwrDnC_RMASK 0x1
825 #define QIB_6120_SerdesCfg0_L1PwrDnD_RMASK 0x1
827 #define QIB_6120_SerdesCfg0_ResetA_RMASK 0x1
829 #define QIB_6120_SerdesCfg0_ResetB_RMASK 0x1
830 #define QIB_6120_SerdesCfg0_ResetC_LSB 0x1
831 #define QIB_6120_SerdesCfg0_ResetC_RMASK 0x1
833 #define QIB_6120_SerdesCfg0_ResetD_RMASK 0x1
839 #define QIB_6120_SerdesStat_BeaconDetA_RMASK 0x1
841 #define QIB_6120_SerdesStat_BeaconDetB_RMASK 0x1
843 #define QIB_6120_SerdesStat_BeaconDetC_RMASK 0x1
845 #define QIB_6120_SerdesStat_BeaconDetD_RMASK 0x1
847 #define QIB_6120_SerdesStat_RxDetA_RMASK 0x1
849 #define QIB_6120_SerdesStat_RxDetB_RMASK 0x1
851 #define QIB_6120_SerdesStat_RxDetC_RMASK 0x1
853 #define QIB_6120_SerdesStat_RxDetD_RMASK 0x1
855 #define QIB_6120_SerdesStat_TxIdleDetA_RMASK 0x1
857 #define QIB_6120_SerdesStat_TxIdleDetB_RMASK 0x1
858 #define QIB_6120_SerdesStat_TxIdleDetC_LSB 0x1
859 #define QIB_6120_SerdesStat_TxIdleDetC_RMASK 0x1
861 #define QIB_6120_SerdesStat_TxIdleDetD_RMASK 0x1
865 #define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_RMASK 0x1
875 #define QIB_6120_XGXSCfg_mdd_30_RMASK 0x1
877 #define QIB_6120_XGXSCfg_xcv_resetn_RMASK 0x1
878 #define QIB_6120_XGXSCfg_Reserved1_LSB 0x1
879 #define QIB_6120_XGXSCfg_Reserved1_RMASK 0x1
881 #define QIB_6120_XGXSCfg_tx_rx_resetn_RMASK 0x1