Lines Matching +full:- +full:eq
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
168 return dev->mthca_flags & MTHCA_FLAG_SRQ ? in async_mask()
173 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in tavor_set_eq_ci() argument
179 * more EQ entries, and we want to avoid the exceedingly in tavor_set_eq_ci()
184 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), in tavor_set_eq_ci()
185 dev->kar + MTHCA_EQ_DOORBELL, in tavor_set_eq_ci()
186 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); in tavor_set_eq_ci()
189 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in arbel_set_eq_ci() argument
194 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); in arbel_set_eq_ci()
199 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in set_eq_ci() argument
202 arbel_set_eq_ci(dev, eq, ci); in set_eq_ci()
204 tavor_set_eq_ci(dev, eq, ci); in set_eq_ci()
210 dev->kar + MTHCA_EQ_DOORBELL, in tavor_eq_req_not()
211 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); in tavor_eq_req_not()
216 writel(eqn_mask, dev->eq_regs.arbel.eq_arm); in arbel_eq_req_not()
223 dev->kar + MTHCA_EQ_DOORBELL, in disarm_cq()
224 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); in disarm_cq()
228 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) in get_eqe() argument
230 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; in get_eqe()
231 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE; in get_eqe()
234 static inline struct mthca_eqe *next_eqe_sw(struct mthca_eq *eq) in next_eqe_sw() argument
237 eqe = get_eqe(eq, eq->cons_index); in next_eqe_sw()
238 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe; in next_eqe_sw()
243 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW; in set_eqe_hw()
253 record.device = &dev->ib_dev; in port_change()
260 static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq) in mthca_eq_int() argument
267 while ((eqe = next_eqe_sw(eq))) { in mthca_eq_int()
269 * Make sure we read EQ entry contents after we've in mthca_eq_int()
274 switch (eqe->type) { in mthca_eq_int()
276 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; in mthca_eq_int()
277 disarm_cq(dev, eq->eqn, disarm_cqn); in mthca_eq_int()
282 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
287 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
292 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
297 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
302 mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff, in mthca_eq_int()
307 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
312 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
317 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
322 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
328 be16_to_cpu(eqe->event.cmd.token), in mthca_eq_int()
329 eqe->event.cmd.status, in mthca_eq_int()
330 be64_to_cpu(eqe->event.cmd.out_param)); in mthca_eq_int()
335 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3, in mthca_eq_int()
336 eqe->subtype == 0x4); in mthca_eq_int()
341 eqe->event.cq_err.syndrome == 1 ? in mthca_eq_int()
343 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); in mthca_eq_int()
344 mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn), in mthca_eq_int()
349 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); in mthca_eq_int()
357 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n", in mthca_eq_int()
358 eqe->type, eqe->subtype, eq->eqn); in mthca_eq_int()
363 ++eq->cons_index; in mthca_eq_int()
379 set_eq_ci(dev, eq, eq->cons_index); in mthca_eq_int()
397 if (dev->eq_table.clr_mask) in mthca_tavor_interrupt()
398 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_tavor_interrupt()
400 ecr = readl(dev->eq_regs.tavor.ecr_base + 4); in mthca_tavor_interrupt()
404 writel(ecr, dev->eq_regs.tavor.ecr_base + in mthca_tavor_interrupt()
405 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4); in mthca_tavor_interrupt()
408 if (ecr & dev->eq_table.eq[i].eqn_mask) { in mthca_tavor_interrupt()
409 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) in mthca_tavor_interrupt()
410 tavor_set_eq_ci(dev, &dev->eq_table.eq[i], in mthca_tavor_interrupt()
411 dev->eq_table.eq[i].cons_index); in mthca_tavor_interrupt()
412 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn); in mthca_tavor_interrupt()
420 struct mthca_eq *eq = eq_ptr; in mthca_tavor_msi_x_interrupt() local
421 struct mthca_dev *dev = eq->dev; in mthca_tavor_msi_x_interrupt()
423 mthca_eq_int(dev, eq); in mthca_tavor_msi_x_interrupt()
424 tavor_set_eq_ci(dev, eq, eq->cons_index); in mthca_tavor_msi_x_interrupt()
425 tavor_eq_req_not(dev, eq->eqn); in mthca_tavor_msi_x_interrupt()
427 /* MSI-X vectors always belong to us */ in mthca_tavor_msi_x_interrupt()
437 if (dev->eq_table.clr_mask) in mthca_arbel_interrupt()
438 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_arbel_interrupt()
441 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) { in mthca_arbel_interrupt()
443 arbel_set_eq_ci(dev, &dev->eq_table.eq[i], in mthca_arbel_interrupt()
444 dev->eq_table.eq[i].cons_index); in mthca_arbel_interrupt()
447 arbel_eq_req_not(dev, dev->eq_table.arm_mask); in mthca_arbel_interrupt()
454 struct mthca_eq *eq = eq_ptr; in mthca_arbel_msi_x_interrupt() local
455 struct mthca_dev *dev = eq->dev; in mthca_arbel_msi_x_interrupt()
457 mthca_eq_int(dev, eq); in mthca_arbel_msi_x_interrupt()
458 arbel_set_eq_ci(dev, eq, eq->cons_index); in mthca_arbel_msi_x_interrupt()
459 arbel_eq_req_not(dev, eq->eqn_mask); in mthca_arbel_msi_x_interrupt()
461 /* MSI-X vectors always belong to us */ in mthca_arbel_msi_x_interrupt()
468 struct mthca_eq *eq) in mthca_create_eq() argument
475 int err = -ENOMEM; in mthca_create_eq()
478 eq->dev = dev; in mthca_create_eq()
479 eq->nent = roundup_pow_of_two(max(nent, 2)); in mthca_create_eq()
480 npages = ALIGN(eq->nent * MTHCA_EQ_ENTRY_SIZE, PAGE_SIZE) / PAGE_SIZE; in mthca_create_eq()
482 eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list), in mthca_create_eq()
484 if (!eq->page_list) in mthca_create_eq()
488 eq->page_list[i].buf = NULL; in mthca_create_eq()
497 eq_context = mailbox->buf; in mthca_create_eq()
500 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, in mthca_create_eq()
502 if (!eq->page_list[i].buf) in mthca_create_eq()
506 dma_unmap_addr_set(&eq->page_list[i], mapping, t); in mthca_create_eq()
508 clear_page(eq->page_list[i].buf); in mthca_create_eq()
511 for (i = 0; i < eq->nent; ++i) in mthca_create_eq()
512 set_eqe_hw(get_eqe(eq, i)); in mthca_create_eq()
514 eq->eqn = mthca_alloc(&dev->eq_table.alloc); in mthca_create_eq()
515 if (eq->eqn == -1) in mthca_create_eq()
518 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num, in mthca_create_eq()
523 &eq->mr); in mthca_create_eq()
528 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK | in mthca_create_eq()
533 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL); in mthca_create_eq()
535 eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24); in mthca_create_eq()
537 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num); in mthca_create_eq()
539 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); in mthca_create_eq()
540 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num); in mthca_create_eq()
542 eq_context->intr = intr; in mthca_create_eq()
543 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey); in mthca_create_eq()
545 err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn); in mthca_create_eq()
554 eq->eqn_mask = swab32(1 << eq->eqn); in mthca_create_eq()
555 eq->cons_index = 0; in mthca_create_eq()
557 dev->eq_table.arm_mask |= eq->eqn_mask; in mthca_create_eq()
559 mthca_dbg(dev, "Allocated EQ %d with %d entries\n", in mthca_create_eq()
560 eq->eqn, eq->nent); in mthca_create_eq()
565 mthca_free_mr(dev, &eq->mr); in mthca_create_eq()
568 mthca_free(&dev->eq_table.alloc, eq->eqn); in mthca_create_eq()
572 if (eq->page_list[i].buf) in mthca_create_eq()
573 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, in mthca_create_eq()
574 eq->page_list[i].buf, in mthca_create_eq()
575 dma_unmap_addr(&eq->page_list[i], in mthca_create_eq()
581 kfree(eq->page_list); in mthca_create_eq()
589 struct mthca_eq *eq) in mthca_free_eq() argument
593 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) / in mthca_free_eq()
601 err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn); in mthca_free_eq()
605 dev->eq_table.arm_mask &= ~eq->eqn_mask; in mthca_free_eq()
608 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); in mthca_free_eq()
612 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4)); in mthca_free_eq()
618 mthca_free_mr(dev, &eq->mr); in mthca_free_eq()
620 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, in mthca_free_eq()
621 eq->page_list[i].buf, in mthca_free_eq()
622 dma_unmap_addr(&eq->page_list[i], mapping)); in mthca_free_eq()
624 kfree(eq->page_list); in mthca_free_eq()
632 if (dev->eq_table.have_irq) in mthca_free_irqs()
633 free_irq(dev->pdev->irq, dev); in mthca_free_irqs()
635 if (dev->eq_table.eq[i].have_irq) { in mthca_free_irqs()
636 free_irq(dev->eq_table.eq[i].msi_x_vector, in mthca_free_irqs()
637 dev->eq_table.eq + i); in mthca_free_irqs()
638 dev->eq_table.eq[i].have_irq = 0; in mthca_free_irqs()
646 phys_addr_t base = pci_resource_start(dev->pdev, 0); in mthca_map_reg()
650 return -ENOMEM; in mthca_map_reg()
659 * We assume that the EQ arm and EQ set CI registers in mthca_map_eq_regs()
665 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & in mthca_map_eq_regs()
666 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE, in mthca_map_eq_regs()
667 &dev->clr_base)) { in mthca_map_eq_regs()
670 return -ENOMEM; in mthca_map_eq_regs()
677 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) & in mthca_map_eq_regs()
678 dev->fw.arbel.eq_arm_base) + 4, 4, in mthca_map_eq_regs()
679 &dev->eq_regs.arbel.eq_arm)) { in mthca_map_eq_regs()
680 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n"); in mthca_map_eq_regs()
681 iounmap(dev->clr_base); in mthca_map_eq_regs()
682 return -ENOMEM; in mthca_map_eq_regs()
685 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & in mthca_map_eq_regs()
686 dev->fw.arbel.eq_set_ci_base, in mthca_map_eq_regs()
688 &dev->eq_regs.arbel.eq_set_ci_base)) { in mthca_map_eq_regs()
689 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n"); in mthca_map_eq_regs()
690 iounmap(dev->eq_regs.arbel.eq_arm); in mthca_map_eq_regs()
691 iounmap(dev->clr_base); in mthca_map_eq_regs()
692 return -ENOMEM; in mthca_map_eq_regs()
696 &dev->clr_base)) { in mthca_map_eq_regs()
699 return -ENOMEM; in mthca_map_eq_regs()
704 &dev->eq_regs.tavor.ecr_base)) { in mthca_map_eq_regs()
707 iounmap(dev->clr_base); in mthca_map_eq_regs()
708 return -ENOMEM; in mthca_map_eq_regs()
719 iounmap(dev->eq_regs.arbel.eq_set_ci_base); in mthca_unmap_eq_regs()
720 iounmap(dev->eq_regs.arbel.eq_arm); in mthca_unmap_eq_regs()
721 iounmap(dev->clr_base); in mthca_unmap_eq_regs()
723 iounmap(dev->eq_regs.tavor.ecr_base); in mthca_unmap_eq_regs()
724 iounmap(dev->clr_base); in mthca_unmap_eq_regs()
733 * We assume that mapping one page is enough for the whole EQ in mthca_map_eq_icm()
735 * we only use 32 EQs and each EQ uses 32 bytes of context in mthca_map_eq_icm()
738 dev->eq_table.icm_virt = icm_virt; in mthca_map_eq_icm()
739 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER); in mthca_map_eq_icm()
740 if (!dev->eq_table.icm_page) in mthca_map_eq_icm()
741 return -ENOMEM; in mthca_map_eq_icm()
742 dev->eq_table.icm_dma = in mthca_map_eq_icm()
743 dma_map_page(&dev->pdev->dev, dev->eq_table.icm_page, 0, in mthca_map_eq_icm()
745 if (dma_mapping_error(&dev->pdev->dev, dev->eq_table.icm_dma)) { in mthca_map_eq_icm()
746 __free_page(dev->eq_table.icm_page); in mthca_map_eq_icm()
747 return -ENOMEM; in mthca_map_eq_icm()
750 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt); in mthca_map_eq_icm()
752 dma_unmap_page(&dev->pdev->dev, dev->eq_table.icm_dma, in mthca_map_eq_icm()
754 __free_page(dev->eq_table.icm_page); in mthca_map_eq_icm()
762 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, 1); in mthca_unmap_eq_icm()
763 dma_unmap_page(&dev->pdev->dev, dev->eq_table.icm_dma, PAGE_SIZE, in mthca_unmap_eq_icm()
765 __free_page(dev->eq_table.icm_page); in mthca_unmap_eq_icm()
774 err = mthca_alloc_init(&dev->eq_table.alloc, in mthca_init_eq_table()
775 dev->limits.num_eqs, in mthca_init_eq_table()
776 dev->limits.num_eqs - 1, in mthca_init_eq_table()
777 dev->limits.reserved_eqs); in mthca_init_eq_table()
785 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { in mthca_init_eq_table()
786 dev->eq_table.clr_mask = 0; in mthca_init_eq_table()
788 dev->eq_table.clr_mask = in mthca_init_eq_table()
789 swab32(1 << (dev->eq_table.inta_pin & 31)); in mthca_init_eq_table()
790 dev->eq_table.clr_int = dev->clr_base + in mthca_init_eq_table()
791 (dev->eq_table.inta_pin < 32 ? 4 : 0); in mthca_init_eq_table()
794 dev->eq_table.arm_mask = 0; in mthca_init_eq_table()
796 intr = dev->eq_table.inta_pin; in mthca_init_eq_table()
798 err = mthca_create_eq(dev, dev->limits.num_cqs + MTHCA_NUM_SPARE_EQE, in mthca_init_eq_table()
799 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr, in mthca_init_eq_table()
800 &dev->eq_table.eq[MTHCA_EQ_COMP]); in mthca_init_eq_table()
805 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr, in mthca_init_eq_table()
806 &dev->eq_table.eq[MTHCA_EQ_ASYNC]); in mthca_init_eq_table()
811 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr, in mthca_init_eq_table()
812 &dev->eq_table.eq[MTHCA_EQ_CMD]); in mthca_init_eq_table()
816 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { in mthca_init_eq_table()
818 [MTHCA_EQ_COMP] = DRV_NAME "-comp", in mthca_init_eq_table()
819 [MTHCA_EQ_ASYNC] = DRV_NAME "-async", in mthca_init_eq_table()
820 [MTHCA_EQ_CMD] = DRV_NAME "-cmd" in mthca_init_eq_table()
824 snprintf(dev->eq_table.eq[i].irq_name, in mthca_init_eq_table()
827 pci_name(dev->pdev)); in mthca_init_eq_table()
828 err = request_irq(dev->eq_table.eq[i].msi_x_vector, in mthca_init_eq_table()
832 0, dev->eq_table.eq[i].irq_name, in mthca_init_eq_table()
833 dev->eq_table.eq + i); in mthca_init_eq_table()
836 dev->eq_table.eq[i].have_irq = 1; in mthca_init_eq_table()
839 snprintf(dev->eq_table.eq[0].irq_name, IB_DEVICE_NAME_MAX, in mthca_init_eq_table()
840 DRV_NAME "@pci:%s", pci_name(dev->pdev)); in mthca_init_eq_table()
841 err = request_irq(dev->pdev->irq, in mthca_init_eq_table()
845 IRQF_SHARED, dev->eq_table.eq[0].irq_name, dev); in mthca_init_eq_table()
848 dev->eq_table.have_irq = 1; in mthca_init_eq_table()
852 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); in mthca_init_eq_table()
854 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", in mthca_init_eq_table()
855 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err); in mthca_init_eq_table()
858 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn); in mthca_init_eq_table()
860 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n", in mthca_init_eq_table()
861 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err); in mthca_init_eq_table()
865 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask); in mthca_init_eq_table()
867 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn); in mthca_init_eq_table()
873 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]); in mthca_init_eq_table()
876 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]); in mthca_init_eq_table()
879 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]); in mthca_init_eq_table()
885 mthca_alloc_cleanup(&dev->eq_table.alloc); in mthca_init_eq_table()
896 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); in mthca_cleanup_eq_table()
898 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn); in mthca_cleanup_eq_table()
901 mthca_free_eq(dev, &dev->eq_table.eq[i]); in mthca_cleanup_eq_table()
905 mthca_alloc_cleanup(&dev->eq_table.alloc); in mthca_cleanup_eq_table()