hw/irdma/defs.h

1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
14 #define IRDMA_PE_DB_SIZE_4M	1
18 #define IRDMA_IRD_HW_SIZE_16	1
25 	IRDMA_IWARP_PROTOCOL_ONLY = 1,
30 #define IRDMA_QP_STATE_IDLE		1
56 #define RDMA_READ_REQ_OPCODE	1
60 #define IRDMA_TERM_SENT		1
65 #define IRDMA_CQP_WAIT_POLL_REGS	1
87 #define IRDMA_TCP_STATE_CLOSED		1
106 #define IRDMA_CQ_TYPE_IWARP	1
123 	((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
126 #define IRDMAQP_TERM_SEND_TERM_ONLY		1
130 #define IRDMA_QP_TYPE_IWARP	1
138 #define IRDMA_CQE_QTYPE_SQ	1
143 #define IRDMA_QP_WQE_MIN_QUANTA 1
148 #define IRDMA_RQ_RSVD	1
150 #define IRDMA_FEATURE_RTS_AE			1ULL
167 	IRDMA_OP_CEQ_DESTROY			= 1,
213 	IRDMA_OP_DELETE_LOCAL_MAC_ENTRY		= 47,
360 	(((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 	(((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
421 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
425 #define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
431 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
440 #define IRDMA_CQPHC_HW_MAJVER_GEN_2 1
476 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
525 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
555 #define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
577 #define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
595 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
615 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
617 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
628 /* Manage Push Page - MPP */
638 /* Upload Context - UCTX */
655 #define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
660 #define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
671 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
687 #define IRDMA_CQPSQ_UPESD_BM_CP_LM 1
704 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
726 #define IRDMAQPC_PMENA BIT_ULL(47)
738 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
746 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
758 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
833 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
834 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
864 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
888 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
914 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
922 		(_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
927 		(_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
932 		(_ceq)->ceqe_base[_pos].buf  \
944 		(_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf  \
949 		((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
967 			(_ring).head = ((_ring).head + 1) % size; \
970 			(_retcode) = -ENOMEM; \
981 			(_retcode) = -ENOMEM; \
989 			(_ring).head = ((_ring).head + 1) % size; \
992 			(_retcode) = -ENOMEM; \
999 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1003 			(_retcode) = -ENOMEM; \
1010 	(_ring).tail = ((_ring).tail + 1) % (_ring).size
1013 	(_ring).head = ((_ring).head + 1) % (_ring).size
1023 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1))  \
1028 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2))  \
1033 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3))  \
1038 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257))  \
1043 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258))  \
1047 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259))  \
1056 		(((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1061 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1066 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1089 enum {	IRDMA_Q_ALIGNMENT_M		 = (128 - 1),
1090 	IRDMA_AEQ_ALIGNMENT_M		 = (256 - 1),
1091 	IRDMA_Q2_ALIGNMENT_M		 = (256 - 1),
1092 	IRDMA_CEQ_ALIGNMENT_M		 = (256 - 1),
1093 	IRDMA_CQ0_ALIGNMENT_M		 = (256 - 1),
1094 	IRDMA_HOST_CTX_ALIGNMENT_M	 = (4 - 1),
1095 	IRDMA_SHADOWAREA_M		 = (128 - 1),
1096 	IRDMA_FPM_QUERY_BUF_ALIGNMENT_M	 = (4 - 1),
1097 	IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1111 	ICRDMA_IWARP_PROTOCOL_ONLY = 1,
1116  * set_64bit_val - set 64 bit value to hw wqe
1127  * set_32bit_val - set 32 bit value to hw wqe
1138  * get_64bit_val - read 64 bit value from wqe
1149  * get_32bit_val - read 32 bit value from wqe