Lines Matching refs:dd
24 int hfi1_pcie_init(struct hfi1_devdata *dd) in hfi1_pcie_init() argument
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
62 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret); in hfi1_pcie_init()
93 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) in hfi1_pcie_ddinit() argument
110 dd_dev_err(dd, "chip PIO range does not match\n"); in hfi1_pcie_ddinit()
114 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
115 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
116 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); in hfi1_pcie_ddinit()
119 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
122 dd->revision = readq(dd->kregbase1 + CCE_REVISION); in hfi1_pcie_ddinit()
123 if (dd->revision == ~(u64)0) { in hfi1_pcie_ddinit()
124 dd_dev_err(dd, "Cannot read chip CSRs\n"); in hfi1_pcie_ddinit()
128 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
129 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); in hfi1_pcie_ddinit()
130 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; in hfi1_pcie_ddinit()
132 dd->kregbase2 = ioremap( in hfi1_pcie_ddinit()
133 addr + dd->base2_start, in hfi1_pcie_ddinit()
134 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
135 if (!dd->kregbase2) { in hfi1_pcie_ddinit()
136 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); in hfi1_pcie_ddinit()
139 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
140 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
142 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
143 if (!dd->piobase) { in hfi1_pcie_ddinit()
144 dd_dev_err(dd, "WC mapping of send buffers failed\n"); in hfi1_pcie_ddinit()
147 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
149 dd->physaddr = addr; /* used for io_remap, etc. */ in hfi1_pcie_ddinit()
155 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, in hfi1_pcie_ddinit()
157 if (!dd->rcvarray_wc) { in hfi1_pcie_ddinit()
158 dd_dev_err(dd, "WC mapping of receive array failed\n"); in hfi1_pcie_ddinit()
161 dd_dev_info(dd, "WC RcvArray: %p for %x\n", in hfi1_pcie_ddinit()
162 dd->rcvarray_wc, rcv_array_count * 8); in hfi1_pcie_ddinit()
164 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ in hfi1_pcie_ddinit()
168 hfi1_pcie_ddcleanup(dd); in hfi1_pcie_ddinit()
177 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) in hfi1_pcie_ddcleanup() argument
179 dd->flags &= ~HFI1_PRESENT; in hfi1_pcie_ddcleanup()
180 if (dd->kregbase1) in hfi1_pcie_ddcleanup()
181 iounmap(dd->kregbase1); in hfi1_pcie_ddcleanup()
182 dd->kregbase1 = NULL; in hfi1_pcie_ddcleanup()
183 if (dd->kregbase2) in hfi1_pcie_ddcleanup()
184 iounmap(dd->kregbase2); in hfi1_pcie_ddcleanup()
185 dd->kregbase2 = NULL; in hfi1_pcie_ddcleanup()
186 if (dd->rcvarray_wc) in hfi1_pcie_ddcleanup()
187 iounmap(dd->rcvarray_wc); in hfi1_pcie_ddcleanup()
188 dd->rcvarray_wc = NULL; in hfi1_pcie_ddcleanup()
189 if (dd->piobase) in hfi1_pcie_ddcleanup()
190 iounmap(dd->piobase); in hfi1_pcie_ddcleanup()
191 dd->piobase = NULL; in hfi1_pcie_ddcleanup()
215 static void update_lbus_info(struct hfi1_devdata *dd) in update_lbus_info() argument
220 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in update_lbus_info()
222 dd_dev_err(dd, "Unable to read from PCI config\n"); in update_lbus_info()
226 dd->lbus_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat); in update_lbus_info()
227 dd->lbus_speed = extract_speed(linkstat); in update_lbus_info()
228 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in update_lbus_info()
229 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); in update_lbus_info()
236 int pcie_speeds(struct hfi1_devdata *dd) in pcie_speeds() argument
239 struct pci_dev *parent = dd->pcidev->bus->self; in pcie_speeds()
242 if (!pci_is_pcie(dd->pcidev)) { in pcie_speeds()
243 dd_dev_err(dd, "Can't find PCI Express capability!\n"); in pcie_speeds()
248 dd->link_gen3_capable = 1; in pcie_speeds()
250 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); in pcie_speeds()
252 dd_dev_err(dd, "Unable to read from PCI config\n"); in pcie_speeds()
257 dd_dev_info(dd, in pcie_speeds()
260 dd->link_gen3_capable = 0; in pcie_speeds()
267 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || in pcie_speeds()
268 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { in pcie_speeds()
269 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); in pcie_speeds()
270 dd->link_gen3_capable = 0; in pcie_speeds()
274 update_lbus_info(dd); in pcie_speeds()
276 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
286 int restore_pci_variables(struct hfi1_devdata *dd) in restore_pci_variables() argument
290 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); in restore_pci_variables()
294 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in restore_pci_variables()
295 dd->pcibar0); in restore_pci_variables()
299 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in restore_pci_variables()
300 dd->pcibar1); in restore_pci_variables()
304 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); in restore_pci_variables()
308 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, in restore_pci_variables()
309 dd->pcie_devctl); in restore_pci_variables()
313 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, in restore_pci_variables()
314 dd->pcie_lnkctl); in restore_pci_variables()
318 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, in restore_pci_variables()
319 dd->pcie_devctl2); in restore_pci_variables()
323 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); in restore_pci_variables()
327 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in restore_pci_variables()
328 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, in restore_pci_variables()
329 dd->pci_tph2); in restore_pci_variables()
336 dd_dev_err(dd, "Unable to write to PCI config\n"); in restore_pci_variables()
345 int save_pci_variables(struct hfi1_devdata *dd) in save_pci_variables() argument
349 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in save_pci_variables()
350 &dd->pcibar0); in save_pci_variables()
354 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in save_pci_variables()
355 &dd->pcibar1); in save_pci_variables()
359 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); in save_pci_variables()
363 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); in save_pci_variables()
367 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, in save_pci_variables()
368 &dd->pcie_devctl); in save_pci_variables()
372 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, in save_pci_variables()
373 &dd->pcie_lnkctl); in save_pci_variables()
377 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, in save_pci_variables()
378 &dd->pcie_devctl2); in save_pci_variables()
382 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); in save_pci_variables()
386 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in save_pci_variables()
387 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, in save_pci_variables()
388 &dd->pci_tph2); in save_pci_variables()
395 dd_dev_err(dd, "Unable to read from PCI config\n"); in save_pci_variables()
412 void tune_pcie_caps(struct hfi1_devdata *dd) in tune_pcie_caps() argument
423 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); in tune_pcie_caps()
425 dd_dev_info(dd, "Enabling PCIe extended tags\n"); in tune_pcie_caps()
427 ret = pcie_capability_write_word(dd->pcidev, in tune_pcie_caps()
430 dd_dev_info(dd, "Unable to write to PCI config\n"); in tune_pcie_caps()
433 parent = dd->pcidev->bus->self; in tune_pcie_caps()
439 dd_dev_info(dd, "Parent not found\n"); in tune_pcie_caps()
443 dd_dev_info(dd, "Parent not root\n"); in tune_pcie_caps()
447 dd_dev_info(dd, "Parent is not PCI Express capable\n"); in tune_pcie_caps()
450 if (!pci_is_pcie(dd->pcidev)) { in tune_pcie_caps()
451 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); in tune_pcie_caps()
457 ep_mpss = dd->pcidev->pcie_mpss; in tune_pcie_caps()
458 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in tune_pcie_caps()
475 pcie_set_mps(dd->pcidev, 128 << ep_mps); in tune_pcie_caps()
489 ep_mrrs = pcie_get_readrq(dd->pcidev); in tune_pcie_caps()
497 pcie_set_readrq(dd->pcidev, ep_mrrs); in tune_pcie_caps()
510 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_error_detected() local
515 dd_dev_info(dd, "State Normal, ignoring\n"); in pci_error_detected()
519 dd_dev_info(dd, "State Frozen, requesting reset\n"); in pci_error_detected()
525 if (dd) { in pci_error_detected()
526 dd_dev_info(dd, "State Permanent Failure, disabling\n"); in pci_error_detected()
528 dd->flags &= ~HFI1_PRESENT; in pci_error_detected()
529 hfi1_disable_after_error(dd); in pci_error_detected()
536 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", in pci_error_detected()
547 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_mmio_enabled() local
550 if (dd && dd->pport) { in pci_mmio_enabled()
551 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); in pci_mmio_enabled()
554 dd_dev_info(dd, in pci_mmio_enabled()
564 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_slot_reset() local
566 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); in pci_slot_reset()
573 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_resume() local
575 dd_dev_info(dd, "HFI1 resume function called\n"); in pci_resume()
581 hfi1_init(dd, 1); /* same as re-init after reset */ in pci_resume()
718 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, in load_eq_table() argument
721 struct pci_dev *pdev = dd->pcidev; in load_eq_table()
738 ret = pci_read_config_dword(dd->pcidev, in load_eq_table()
741 dd_dev_err(dd, "Unable to read from PCI config\n"); in load_eq_table()
749 dd_dev_err(dd, in load_eq_table()
751 dd_dev_err(dd, " prec attn post\n"); in load_eq_table()
753 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", in load_eq_table()
756 dd_dev_err(dd, " %02x %02x %02x\n", in load_eq_table()
771 static void pcie_post_steps(struct hfi1_devdata *dd) in pcie_post_steps() argument
775 set_sbus_fast_mode(dd); in pcie_post_steps()
784 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], in pcie_post_steps()
788 clear_sbus_fast_mode(dd); in pcie_post_steps()
797 static int trigger_sbr(struct hfi1_devdata *dd) in trigger_sbr() argument
799 struct pci_dev *dev = dd->pcidev; in trigger_sbr()
804 dd_dev_err(dd, "%s: no parent device\n", __func__); in trigger_sbr()
811 dd_dev_err(dd, in trigger_sbr()
828 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, in write_gasket_interrupt() argument
831 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), in write_gasket_interrupt()
839 static void arm_gasket_logic(struct hfi1_devdata *dd) in arm_gasket_logic() argument
843 reg = (((u64)1 << dd->hfi1_id) << in arm_gasket_logic()
845 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << in arm_gasket_logic()
850 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); in arm_gasket_logic()
852 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
874 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) in write_xmt_margin() argument
882 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); in write_xmt_margin()
892 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ in write_xmt_margin()
906 if (is_ax(dd)) { in write_xmt_margin()
925 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); in write_xmt_margin()
928 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", in write_xmt_margin()
935 int do_pcie_gen3_transition(struct hfi1_devdata *dd) in do_pcie_gen3_transition() argument
937 struct pci_dev *parent = dd->pcidev->bus->self; in do_pcie_gen3_transition()
957 if (dd->icode != ICODE_RTL_SILICON) in do_pcie_gen3_transition()
971 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); in do_pcie_gen3_transition()
976 if (dd->lbus_speed == target_speed) { in do_pcie_gen3_transition()
977 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, in do_pcie_gen3_transition()
989 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", in do_pcie_gen3_transition()
995 target_width = dd->lbus_width; in do_pcie_gen3_transition()
1005 if (pcie_target == 3 && !dd->link_gen3_capable) { in do_pcie_gen3_transition()
1006 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); in do_pcie_gen3_transition()
1012 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); in do_pcie_gen3_transition()
1014 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", in do_pcie_gen3_transition()
1020 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1022 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in do_pcie_gen3_transition()
1024 dd_dev_info(dd, "%s: Disabled therm polling\n", in do_pcie_gen3_transition()
1033 dd_dev_info(dd, "%s: downloading firmware\n", __func__); in do_pcie_gen3_transition()
1034 ret = load_pcie_firmware(dd); in do_pcie_gen3_transition()
1042 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); in do_pcie_gen3_transition()
1052 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); in do_pcie_gen3_transition()
1063 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1073 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1083 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ in do_pcie_gen3_transition()
1104 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, in do_pcie_gen3_transition()
1109 ret = load_eq_table(dd, eq, fs, div); in do_pcie_gen3_transition()
1121 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", in do_pcie_gen3_transition()
1125 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); in do_pcie_gen3_transition()
1126 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, in do_pcie_gen3_transition()
1135 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); in do_pcie_gen3_transition()
1136 pcie_post_steps(dd); in do_pcie_gen3_transition()
1142 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); in do_pcie_gen3_transition()
1145 write_gasket_interrupt(dd, intnum++, 0x0026, in do_pcie_gen3_transition()
1151 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); in do_pcie_gen3_transition()
1161 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); in do_pcie_gen3_transition()
1162 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); in do_pcie_gen3_transition()
1163 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); in do_pcie_gen3_transition()
1164 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); in do_pcie_gen3_transition()
1168 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); in do_pcie_gen3_transition()
1173 write_xmt_margin(dd, __func__); in do_pcie_gen3_transition()
1179 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); in do_pcie_gen3_transition()
1180 aspm_hw_disable_l1(dd); in do_pcie_gen3_transition()
1198 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); in do_pcie_gen3_transition()
1201 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1206 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1212 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1217 dd_dev_err(dd, "Unable to write to PCI config\n"); in do_pcie_gen3_transition()
1222 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); in do_pcie_gen3_transition()
1225 dd_dev_info(dd, "%s: setting target link speed\n", __func__); in do_pcie_gen3_transition()
1226 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); in do_pcie_gen3_transition()
1228 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1233 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1237 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1239 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); in do_pcie_gen3_transition()
1241 dd_dev_err(dd, "Unable to write to PCI config\n"); in do_pcie_gen3_transition()
1248 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in do_pcie_gen3_transition()
1249 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1251 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1253 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); in do_pcie_gen3_transition()
1254 arm_gasket_logic(dd); in do_pcie_gen3_transition()
1269 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); in do_pcie_gen3_transition()
1270 ret = trigger_sbr(dd); in do_pcie_gen3_transition()
1277 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); in do_pcie_gen3_transition()
1279 dd_dev_info(dd, in do_pcie_gen3_transition()
1286 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition()
1293 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); in do_pcie_gen3_transition()
1294 ret = restore_pci_variables(dd); in do_pcie_gen3_transition()
1296 dd_dev_err(dd, "%s: Could not restore PCI variables\n", in do_pcie_gen3_transition()
1303 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); in do_pcie_gen3_transition()
1315 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
1316 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); in do_pcie_gen3_transition()
1318 dd_dev_err(dd, "SBR failed - unable to read from device\n"); in do_pcie_gen3_transition()
1325 write_csr(dd, CCE_DC_CTRL, 0); in do_pcie_gen3_transition()
1328 setextled(dd, 0); in do_pcie_gen3_transition()
1331 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition()
1333 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1338 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1343 if ((status & (1 << dd->hfi1_id)) == 0) { in do_pcie_gen3_transition()
1344 dd_dev_err(dd, in do_pcie_gen3_transition()
1346 __func__, status, 1 << dd->hfi1_id); in do_pcie_gen3_transition()
1355 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); in do_pcie_gen3_transition()
1361 update_lbus_info(dd); in do_pcie_gen3_transition()
1362 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, in do_pcie_gen3_transition()
1363 dd->lbus_info); in do_pcie_gen3_transition()
1365 if (dd->lbus_speed != target_speed || in do_pcie_gen3_transition()
1366 dd->lbus_width < target_width) { /* not target */ in do_pcie_gen3_transition()
1369 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n", in do_pcie_gen3_transition()
1381 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in do_pcie_gen3_transition()
1383 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()
1386 release_chip_resource(dd, CR_SBUS); in do_pcie_gen3_transition()
1390 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); in do_pcie_gen3_transition()
1394 dd_dev_info(dd, "%s: done\n", __func__); in do_pcie_gen3_transition()