Lines Matching full:adc
3 * This file is part of STM32 ADC driver
31 #include "stm32-adc-core.h"
36 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
94 * struct stm32_adc_ic - ADC internal channels
112 * struct stm32_adc_trig_info - ADC trigger info
122 * struct stm32_adc_calib - optional adc calibration data
132 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
144 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data
210 * @smp_cycles: programmable sampling time (ADC clock cycles)
232 * struct stm32_adc - private data of each ADC IIO instance
233 * @common: reference to ADC block common data
234 * @offset: ADC instance register offset in ADC block
238 * @clk: clock for this adc instance
239 * @irq: interrupt for this adc instance
293 * struct stm32_adc_info - stm32 ADC, per instance config data
410 /* STM32F4 programmable sampling time (ADC clock cycles) */
504 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
525 /* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */
571 * STM32 ADC registers access routines
572 * @adc: stm32 adc instance
573 * @reg: reg offset in adc instance
578 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) in stm32_adc_readl() argument
580 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
583 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
589 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) in stm32_adc_readw() argument
591 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
594 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) in stm32_adc_writel() argument
596 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
599 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits() argument
603 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
604 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); in stm32_adc_set_bits()
605 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
608 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits_common() argument
610 spin_lock(&adc->common->lock); in stm32_adc_set_bits_common()
611 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, in stm32_adc_set_bits_common()
612 adc->common->base + reg); in stm32_adc_set_bits_common()
613 spin_unlock(&adc->common->lock); in stm32_adc_set_bits_common()
616 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits() argument
620 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
621 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); in stm32_adc_clr_bits()
622 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
625 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits_common() argument
627 spin_lock(&adc->common->lock); in stm32_adc_clr_bits_common()
628 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, in stm32_adc_clr_bits_common()
629 adc->common->base + reg); in stm32_adc_clr_bits_common()
630 spin_unlock(&adc->common->lock); in stm32_adc_clr_bits_common()
635 * @adc: stm32 adc instance
637 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) in stm32_adc_conv_irq_enable() argument
639 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
640 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
645 * @adc: stm32 adc instance
647 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) in stm32_adc_conv_irq_disable() argument
649 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
650 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
653 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) in stm32_adc_ovr_irq_enable() argument
655 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_enable()
656 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_enable()
659 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) in stm32_adc_ovr_irq_disable() argument
661 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_disable()
662 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_disable()
665 static void stm32_adc_set_res(struct stm32_adc *adc) in stm32_adc_set_res() argument
667 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res()
670 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
671 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
672 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
678 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_stop() local
680 if (adc->cfg->unprepare) in stm32_adc_hw_stop()
681 adc->cfg->unprepare(indio_dev); in stm32_adc_hw_stop()
683 clk_disable_unprepare(adc->clk); in stm32_adc_hw_stop()
691 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_start() local
694 ret = clk_prepare_enable(adc->clk); in stm32_adc_hw_start()
698 stm32_adc_set_res(adc); in stm32_adc_hw_start()
700 if (adc->cfg->prepare) { in stm32_adc_hw_start()
701 ret = adc->cfg->prepare(indio_dev); in stm32_adc_hw_start()
709 clk_disable_unprepare(adc->clk); in stm32_adc_hw_start()
716 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_int_ch_enable() local
720 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_enable()
726 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg, in stm32_adc_int_ch_enable()
727 adc->cfg->regs->or_vddcore.mask); in stm32_adc_int_ch_enable()
731 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg, in stm32_adc_int_ch_enable()
732 adc->cfg->regs->or_vddcpu.mask); in stm32_adc_int_ch_enable()
736 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, in stm32_adc_int_ch_enable()
737 adc->cfg->regs->or_vddq_ddr.mask); in stm32_adc_int_ch_enable()
741 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_enable()
742 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_enable()
746 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_enable()
747 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_enable()
753 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) in stm32_adc_int_ch_disable() argument
758 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_disable()
763 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg, in stm32_adc_int_ch_disable()
764 adc->cfg->regs->or_vddcore.mask); in stm32_adc_int_ch_disable()
767 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg, in stm32_adc_int_ch_disable()
768 adc->cfg->regs->or_vddcpu.mask); in stm32_adc_int_ch_disable()
771 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, in stm32_adc_int_ch_disable()
772 adc->cfg->regs->or_vddq_ddr.mask); in stm32_adc_int_ch_disable()
775 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_disable()
776 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_disable()
779 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_disable()
780 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_disable()
793 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
798 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_start_conv() local
800 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_start_conv()
803 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_start_conv()
806 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); in stm32f4_adc_start_conv()
812 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) in stm32f4_adc_start_conv()
813 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); in stm32f4_adc_start_conv()
818 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_stop_conv() local
820 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); in stm32f4_adc_stop_conv()
821 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); in stm32f4_adc_stop_conv()
823 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_stop_conv()
824 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_stop_conv()
830 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_irq_clear() local
832 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32f4_adc_irq_clear()
837 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_start_conv() local
847 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
848 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); in stm32h7_adc_start_conv()
850 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); in stm32h7_adc_start_conv()
851 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
853 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32h7_adc_start_conv()
858 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_stop_conv() local
862 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); in stm32h7_adc_stop_conv()
871 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); in stm32h7_adc_stop_conv()
876 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_irq_clear() local
878 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32h7_adc_irq_clear()
883 struct stm32_adc *adc = iio_priv(indio_dev); in stm32mp13_adc_start_conv() local
886 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR, in stm32mp13_adc_start_conv()
889 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32mp13_adc_start_conv()
894 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_exit_pwr_down() local
898 /* Exit deep power down, then enable ADC voltage regulator */ in stm32h7_adc_exit_pwr_down()
899 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
900 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); in stm32h7_adc_exit_pwr_down()
902 if (adc->cfg->has_boostmode && in stm32h7_adc_exit_pwr_down()
903 adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
904 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_exit_pwr_down()
907 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
916 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
923 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) in stm32h7_adc_enter_pwr_down() argument
925 if (adc->cfg->has_boostmode) in stm32h7_adc_enter_pwr_down()
926 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_enter_pwr_down()
928 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ in stm32h7_adc_enter_pwr_down()
929 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_enter_pwr_down()
934 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_enable() local
938 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); in stm32h7_adc_enable()
940 /* Poll for ADRDY to be set (after adc startup time) */ in stm32h7_adc_enable()
945 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_enable()
946 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
949 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); in stm32h7_adc_enable()
957 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_disable() local
961 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) in stm32h7_adc_disable()
964 /* Disable ADC and wait until it's effectively disabled */ in stm32h7_adc_disable()
965 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_disable()
976 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
980 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_read_selfcalib() local
988 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_read_selfcalib()
999 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_read_selfcalib()
1000 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
1001 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
1005 adc->cal.lincal_saved = true; in stm32h7_adc_read_selfcalib()
1013 * Note: ADC must be enabled, with no on-going conversions.
1017 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_restore_selfcalib() local
1028 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
1029 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); in stm32h7_adc_restore_selfcalib()
1030 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
1046 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
1054 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_restore_selfcalib()
1055 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
1067 * Fixed timeout value for ADC calibration.
1072 * - 131,072 ADC clock cycle for the linear calibration
1073 * - 20 ADC clock cycle for the offset calibration
1080 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
1083 * Note: Must be called once ADC is out of power down.
1090 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_selfcalib() local
1095 if (adc->cfg->has_linearcal && do_lincal) in stm32h7_adc_selfcalib()
1097 /* ADC must be disabled for calibration */ in stm32h7_adc_selfcalib()
1105 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1108 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1123 stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1124 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1135 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1150 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_check_selfcalib() local
1153 if (adc->cal.lincal_saved) in stm32h7_adc_check_selfcalib()
1157 * Check if linear calibration factors are available in ADC registers, in stm32h7_adc_check_selfcalib()
1160 val = stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_LINCALRDYW_MASK; in stm32h7_adc_check_selfcalib()
1168 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
1171 * Configure channels as single ended or differential before enabling ADC.
1172 * Enable ADC.
1180 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_prepare() local
1188 if (adc->cfg->has_linearcal) in stm32h7_adc_prepare()
1198 stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel); in stm32h7_adc_prepare()
1204 if (adc->cfg->has_linearcal) { in stm32h7_adc_prepare()
1205 if (!adc->cal.lincal_saved) in stm32h7_adc_prepare()
1214 if (adc->cfg->has_presel) in stm32h7_adc_prepare()
1215 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
1222 stm32_adc_int_ch_disable(adc); in stm32h7_adc_prepare()
1224 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_prepare()
1231 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_unprepare() local
1233 if (adc->cfg->has_presel) in stm32h7_adc_unprepare()
1234 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); in stm32h7_adc_unprepare()
1236 stm32_adc_int_ch_disable(adc); in stm32h7_adc_unprepare()
1237 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_unprepare()
1247 * Configure ADC scan sequence based on selected channels in scan_mask.
1254 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_conf_scan_seq() local
1255 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
1261 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
1262 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
1277 val = stm32_adc_readl(adc, sqr[i].reg); in stm32_adc_conf_scan_seq()
1280 stm32_adc_writel(adc, sqr[i].reg, val); in stm32_adc_conf_scan_seq()
1287 val = stm32_adc_readl(adc, sqr[0].reg); in stm32_adc_conf_scan_seq()
1290 stm32_adc_writel(adc, sqr[0].reg, val); in stm32_adc_conf_scan_seq()
1305 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_extsel() local
1309 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
1316 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
1317 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
1336 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig() local
1348 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1351 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1352 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1353 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1354 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1355 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1356 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1357 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1366 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig_pol() local
1368 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1376 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_pol() local
1378 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1408 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_single_conv() local
1410 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1415 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1417 adc->bufi = 0; in stm32_adc_single_conv()
1424 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1425 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1428 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1431 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1434 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1437 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1439 stm32_adc_conv_irq_enable(adc); in stm32_adc_single_conv()
1441 adc->cfg->start_conv(indio_dev, false); in stm32_adc_single_conv()
1444 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1450 *res = adc->buffer[0]; in stm32_adc_single_conv()
1454 adc->cfg->stop_conv(indio_dev); in stm32_adc_single_conv()
1456 stm32_adc_conv_irq_disable(adc); in stm32_adc_single_conv()
1468 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_read_raw() local
1483 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; in stm32_adc_read_raw()
1490 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1493 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1513 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_irq_clear() local
1515 adc->cfg->irq_clear(indio_dev, msk); in stm32_adc_irq_clear()
1521 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_threaded_isr() local
1522 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_threaded_isr()
1523 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_threaded_isr()
1529 * This requires to stop ADC first. OVR bit state in ISR, in stm32_adc_threaded_isr()
1532 adc->cfg->stop_conv(indio_dev); in stm32_adc_threaded_isr()
1544 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_isr() local
1545 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1546 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1556 stm32_adc_ovr_irq_disable(adc); in stm32_adc_isr()
1557 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1563 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1565 adc->bufi++; in stm32_adc_isr()
1566 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1567 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1571 complete(&adc->completion); in stm32_adc_isr()
1580 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1584 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1595 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_watermark() local
1606 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1614 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_update_scan_mode() local
1622 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); in stm32_adc_update_scan_mode()
1650 * To read a value from an ADC register:
1651 * echo [ADC reg offset] > direct_reg_access
1654 * To write a value in a ADC register:
1661 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_reg_access() local
1670 stm32_adc_writel(adc, reg, writeval); in stm32_adc_debugfs_reg_access()
1672 *readval = stm32_adc_readl(adc, reg); in stm32_adc_debugfs_reg_access()
1689 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) in stm32_adc_dma_residue() argument
1694 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1695 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1699 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1703 if (i >= adc->bufi) in stm32_adc_dma_residue()
1704 size = i - adc->bufi; in stm32_adc_dma_residue()
1706 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1717 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_buffer_done() local
1718 int residue = stm32_adc_dma_residue(adc); in stm32_adc_dma_buffer_done()
1729 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1732 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1737 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1738 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1739 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1745 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_start() local
1750 if (!adc->dma_chan) in stm32_adc_dma_start()
1754 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1757 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1758 adc->rx_dma_buf, in stm32_adc_dma_start()
1759 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1771 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1776 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1783 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_postenable() local
1803 /* Reset adc buffer index */ in stm32_adc_buffer_postenable()
1804 adc->bufi = 0; in stm32_adc_buffer_postenable()
1806 stm32_adc_ovr_irq_enable(adc); in stm32_adc_buffer_postenable()
1808 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1809 stm32_adc_conv_irq_enable(adc); in stm32_adc_buffer_postenable()
1811 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1826 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_predisable() local
1829 adc->cfg->stop_conv(indio_dev); in stm32_adc_buffer_predisable()
1830 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1831 stm32_adc_conv_irq_disable(adc); in stm32_adc_buffer_predisable()
1833 stm32_adc_ovr_irq_disable(adc); in stm32_adc_buffer_predisable()
1835 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1836 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1856 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_trigger_handler() local
1858 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
1861 adc->bufi = 0; in stm32_adc_trigger_handler()
1862 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, in stm32_adc_trigger_handler()
1867 stm32_adc_conv_irq_enable(adc); in stm32_adc_trigger_handler()
1885 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_init() local
1887 struct stm32_adc_calib *cal = &adc->cal; in stm32_adc_debugfs_init()
1891 if (!adc->cfg->has_linearcal) in stm32_adc_debugfs_init()
1903 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_fw_get_resolution() local
1908 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_fw_get_resolution()
1910 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_fw_get_resolution()
1911 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_fw_get_resolution()
1913 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_fw_get_resolution()
1919 adc->res = i; in stm32_adc_fw_get_resolution()
1924 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) in stm32_adc_smpr_init() argument
1926 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
1935 if (channel == adc->int_ch[i] && adc->int_ch[i] != STM32_ADC_INT_CH_NONE) in stm32_adc_smpr_init()
1936 smp_ns = max(smp_ns, adc->cfg->ts_int_ch[i]); in stm32_adc_smpr_init()
1938 /* Determine sampling time (ADC clock cycles) */ in stm32_adc_smpr_init()
1939 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
1941 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
1947 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
1954 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_init_one() local
1955 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
1969 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) in stm32_adc_chan_init_one()
1976 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
1981 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1984 adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask; in stm32_adc_chan_init_one()
1986 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
1990 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) in stm32_adc_get_legacy_chan_count() argument
1993 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_get_legacy_chan_count()
1998 ret = device_property_count_u32(dev, "st,adc-channels"); in stm32_adc_get_legacy_chan_count()
2000 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_get_legacy_chan_count()
2007 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret in stm32_adc_get_legacy_chan_count()
2010 ret = device_property_count_u32(dev, "st,adc-diff-channels"); in stm32_adc_get_legacy_chan_count()
2014 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_get_legacy_chan_count()
2017 adc->num_diff = ret; in stm32_adc_get_legacy_chan_count()
2023 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); in stm32_adc_get_legacy_chan_count()
2024 if (adc->nsmps > 1 && adc->nsmps != num_channels) { in stm32_adc_get_legacy_chan_count()
2033 struct stm32_adc *adc, in stm32_adc_legacy_chan_init() argument
2037 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_legacy_chan_init()
2040 u32 num_diff = adc->num_diff; in stm32_adc_legacy_chan_init()
2047 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", in stm32_adc_legacy_chan_init()
2069 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se); in stm32_adc_legacy_chan_init()
2071 dev_err(&indio_dev->dev, "Failed to get st,adc-channels %d\n", ret); in stm32_adc_legacy_chan_init()
2096 if (adc->nsmps > 0) { in stm32_adc_legacy_chan_init()
2098 smps, adc->nsmps); in stm32_adc_legacy_chan_init()
2111 if (i < adc->nsmps) in stm32_adc_legacy_chan_init()
2115 stm32_adc_smpr_init(adc, channels[i].channel, smp); in stm32_adc_legacy_chan_init()
2124 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_populate_int_ch() local
2133 if (!adc->cfg->regs->or_vddcore.reg) in stm32_adc_populate_int_ch()
2138 if (!adc->cfg->regs->or_vddcpu.reg) in stm32_adc_populate_int_ch()
2143 if (!adc->cfg->regs->or_vddq_ddr.reg) in stm32_adc_populate_int_ch()
2148 if (!adc->cfg->regs->ccr_vref.reg) in stm32_adc_populate_int_ch()
2153 if (!adc->cfg->regs->ccr_vbat.reg) in stm32_adc_populate_int_ch()
2160 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2177 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2178 adc->vrefint.vrefint_cal = vrefint; in stm32_adc_populate_int_ch()
2186 struct stm32_adc *adc, in stm32_adc_generic_chan_init() argument
2189 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_generic_chan_init()
2212 strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); in stm32_adc_generic_chan_init()
2257 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); in stm32_adc_generic_chan_init()
2259 stm32_adc_smpr_init(adc, vin[1], val); in stm32_adc_generic_chan_init()
2274 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_fw_init() local
2275 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_fw_init()
2281 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; in stm32_adc_chan_fw_init()
2288 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); in stm32_adc_chan_fw_init()
2314 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, in stm32_adc_chan_fw_init()
2317 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); in stm32_adc_chan_fw_init()
2343 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_request() local
2347 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
2348 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
2349 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
2355 adc->dma_chan = NULL; in stm32_adc_dma_request()
2359 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
2361 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
2362 if (!adc->rx_buf) { in stm32_adc_dma_request()
2369 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
2370 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
2373 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
2380 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
2381 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
2383 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
2393 struct stm32_adc *adc; in stm32_adc_probe() local
2397 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
2401 adc = iio_priv(indio_dev); in stm32_adc_probe()
2402 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
2403 spin_lock_init(&adc->lock); in stm32_adc_probe()
2404 init_completion(&adc->completion); in stm32_adc_probe()
2405 adc->cfg = device_get_match_data(dev); in stm32_adc_probe()
2414 ret = device_property_read_u32(dev, "reg", &adc->offset); in stm32_adc_probe()
2420 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
2421 if (adc->irq < 0) in stm32_adc_probe()
2422 return adc->irq; in stm32_adc_probe()
2424 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
2432 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
2433 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
2434 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
2435 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
2436 adc->clk = NULL; in stm32_adc_probe()
2451 if (!adc->dma_chan) { in stm32_adc_probe()
2472 /* Get stm32-adc-core PM online */ in stm32_adc_probe()
2507 if (adc->dma_chan) { in stm32_adc_probe()
2508 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
2510 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
2511 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
2520 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_remove() local
2530 if (adc->dma_chan) { in stm32_adc_remove()
2531 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
2533 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
2534 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
2653 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2654 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2655 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2656 { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg },
2665 .name = "stm32-adc",
2673 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2675 MODULE_ALIAS("platform:stm32-adc");