Lines Matching +full:adc +full:- +full:vref
1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 ADC driver
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
29 #include "stm32-adc-core.h"
45 * struct stm32_adc_common_regs - stm32 common registers
50 * @ier: interrupt enable register offset for each adc
65 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
69 * @ipid: adc identification number
72 * @num_adcs: maximum number of ADC instances in the common registers
85 * struct stm32_adc_priv - stm32 ADC core private data
86 * @irq: irq(s) for ADC block
87 * @nb_adc_max: actual maximum number of instance per ADC block
95 * @vref: regulator reference
99 * @common: common data for all ADC instances
113 struct regulator *vref; member
127 /* STM32F4 ADC internal common clock prescaler division ratios */
131 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
133 * @priv: stm32 ADC core private data
134 * Select clock prescaler used for analog conversions, before using ADC.
144 if (!priv->aclk) { in stm32f4_adc_clk_sel()
145 dev_err(&pdev->dev, "No 'adc' clock found\n"); in stm32f4_adc_clk_sel()
146 return -ENOENT; in stm32f4_adc_clk_sel()
149 rate = clk_get_rate(priv->aclk); in stm32f4_adc_clk_sel()
151 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); in stm32f4_adc_clk_sel()
152 return -EINVAL; in stm32f4_adc_clk_sel()
156 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) in stm32f4_adc_clk_sel()
160 dev_err(&pdev->dev, "adc clk selection failed\n"); in stm32f4_adc_clk_sel()
161 return -EINVAL; in stm32f4_adc_clk_sel()
164 priv->common.rate = rate / stm32f4_pclk_div[i]; in stm32f4_adc_clk_sel()
165 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); in stm32f4_adc_clk_sel()
168 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); in stm32f4_adc_clk_sel()
170 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", in stm32f4_adc_clk_sel()
171 priv->common.rate / 1000); in stm32f4_adc_clk_sel()
177 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
178 * @ckmode: ADC clock mode, Async or sync with prescaler.
215 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ in stm32h7_adc_clk_sel()
216 if (!priv->bclk) { in stm32h7_adc_clk_sel()
217 dev_err(&pdev->dev, "No 'bus' clock found\n"); in stm32h7_adc_clk_sel()
218 return -ENOENT; in stm32h7_adc_clk_sel()
222 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. in stm32h7_adc_clk_sel()
223 * So, choice is to have bus clock mandatory and adc clock optional. in stm32h7_adc_clk_sel()
224 * If optional 'adc' clock has been found, then try to use it first. in stm32h7_adc_clk_sel()
226 if (priv->aclk) { in stm32h7_adc_clk_sel()
231 rate = clk_get_rate(priv->aclk); in stm32h7_adc_clk_sel()
233 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); in stm32h7_adc_clk_sel()
234 return -EINVAL; in stm32h7_adc_clk_sel()
238 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); in stm32h7_adc_clk_sel()
240 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); in stm32h7_adc_clk_sel()
257 if ((rate / div) <= priv->max_clk_rate) in stm32h7_adc_clk_sel()
263 rate = clk_get_rate(priv->bclk); in stm32h7_adc_clk_sel()
265 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); in stm32h7_adc_clk_sel()
266 return -EINVAL; in stm32h7_adc_clk_sel()
269 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); in stm32h7_adc_clk_sel()
271 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); in stm32h7_adc_clk_sel()
284 if ((rate / div) <= priv->max_clk_rate) in stm32h7_adc_clk_sel()
288 dev_err(&pdev->dev, "adc clk selection failed\n"); in stm32h7_adc_clk_sel()
289 return -EINVAL; in stm32h7_adc_clk_sel()
292 /* rate used later by each ADC instance to control BOOST mode */ in stm32h7_adc_clk_sel()
293 priv->common.rate = rate / div; in stm32h7_adc_clk_sel()
296 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); in stm32h7_adc_clk_sel()
300 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); in stm32h7_adc_clk_sel()
302 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", in stm32h7_adc_clk_sel()
303 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); in stm32h7_adc_clk_sel()
343 unsigned int adc) in stm32_adc_eoc_enabled() argument
345 u32 ier, offset = stm32_adc_offset[adc]; in stm32_adc_eoc_enabled()
347 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); in stm32_adc_eoc_enabled()
349 return ier & priv->cfg->regs->eocie_msk; in stm32_adc_eoc_enabled()
352 /* ADC common interrupt for all instances */
361 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); in stm32_adc_irq_handler()
367 * - an ADC configured to use DMA (EOC triggers the DMA request, and in stm32_adc_irq_handler()
369 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must in stm32_adc_irq_handler()
373 * IRQ-enabled ADCs). in stm32_adc_irq_handler()
375 for (i = 0; i < priv->nb_adc_max; i++) { in stm32_adc_irq_handler()
376 if ((status & priv->cfg->regs->eoc_msk[i] && in stm32_adc_irq_handler()
378 (status & priv->cfg->regs->ovr_msk[i])) in stm32_adc_irq_handler()
379 generic_handle_domain_irq(priv->domain, i); in stm32_adc_irq_handler()
388 irq_set_chip_data(irq, d->host_data); in stm32_adc_domain_map()
409 struct device_node *np = pdev->dev.of_node; in stm32_adc_irq_probe()
414 * - stm32f4/h7 shares a common interrupt line. in stm32_adc_irq_probe()
415 * - stm32mp1, has one line per ADC in stm32_adc_irq_probe()
417 for (i = 0; i < priv->cfg->num_irqs; i++) { in stm32_adc_irq_probe()
418 priv->irq[i] = platform_get_irq(pdev, i); in stm32_adc_irq_probe()
419 if (priv->irq[i] < 0) in stm32_adc_irq_probe()
420 return priv->irq[i]; in stm32_adc_irq_probe()
423 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, in stm32_adc_irq_probe()
426 if (!priv->domain) { in stm32_adc_irq_probe()
427 dev_err(&pdev->dev, "Failed to add irq domain\n"); in stm32_adc_irq_probe()
428 return -ENOMEM; in stm32_adc_irq_probe()
431 for (i = 0; i < priv->cfg->num_irqs; i++) { in stm32_adc_irq_probe()
432 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); in stm32_adc_irq_probe()
433 irq_set_handler_data(priv->irq[i], priv); in stm32_adc_irq_probe()
445 for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++) in stm32_adc_irq_remove()
446 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); in stm32_adc_irq_remove()
447 irq_domain_remove(priv->domain); in stm32_adc_irq_remove()
449 for (i = 0; i < priv->cfg->num_irqs; i++) in stm32_adc_irq_remove()
450 irq_set_chained_handler(priv->irq[i], NULL); in stm32_adc_irq_remove()
459 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog in stm32_adc_core_switches_supply_en()
462 * - Voltage booster can be used, to get full ADC performances in stm32_adc_core_switches_supply_en()
464 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). in stm32_adc_core_switches_supply_en()
467 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) in stm32_adc_core_switches_supply_en()
468 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 in stm32_adc_core_switches_supply_en()
469 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) in stm32_adc_core_switches_supply_en()
471 if (priv->vdda_uv < 2700000) { in stm32_adc_core_switches_supply_en()
472 if (priv->syscfg && priv->vdd_uv > 2700000) { in stm32_adc_core_switches_supply_en()
473 ret = regulator_enable(priv->vdd); in stm32_adc_core_switches_supply_en()
479 ret = regmap_write(priv->syscfg, in stm32_adc_core_switches_supply_en()
483 regulator_disable(priv->vdd); in stm32_adc_core_switches_supply_en()
492 if (priv->booster) { in stm32_adc_core_switches_supply_en()
494 * This is optional, as this is a trade-off between in stm32_adc_core_switches_supply_en()
497 ret = regulator_enable(priv->booster); in stm32_adc_core_switches_supply_en()
510 priv->vdda_uv); in stm32_adc_core_switches_supply_en()
517 if (priv->vdda_uv < 2700000) { in stm32_adc_core_switches_supply_dis()
518 if (priv->syscfg && priv->vdd_uv > 2700000) { in stm32_adc_core_switches_supply_dis()
519 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, in stm32_adc_core_switches_supply_dis()
521 regulator_disable(priv->vdd); in stm32_adc_core_switches_supply_dis()
524 if (priv->booster) in stm32_adc_core_switches_supply_dis()
525 regulator_disable(priv->booster); in stm32_adc_core_switches_supply_dis()
535 ret = regulator_enable(priv->vdda); in stm32_adc_core_hw_start()
541 ret = regulator_get_voltage(priv->vdda); in stm32_adc_core_hw_start()
546 priv->vdda_uv = ret; in stm32_adc_core_hw_start()
552 ret = regulator_enable(priv->vref); in stm32_adc_core_hw_start()
554 dev_err(dev, "vref enable failed\n"); in stm32_adc_core_hw_start()
558 ret = clk_prepare_enable(priv->bclk); in stm32_adc_core_hw_start()
564 ret = clk_prepare_enable(priv->aclk); in stm32_adc_core_hw_start()
566 dev_err(dev, "adc clk enable failed\n"); in stm32_adc_core_hw_start()
570 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); in stm32_adc_core_hw_start()
575 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_start()
577 regulator_disable(priv->vref); in stm32_adc_core_hw_start()
581 regulator_disable(priv->vdda); in stm32_adc_core_hw_start()
592 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); in stm32_adc_core_hw_stop()
593 clk_disable_unprepare(priv->aclk); in stm32_adc_core_hw_stop()
594 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_stop()
595 regulator_disable(priv->vref); in stm32_adc_core_hw_stop()
597 regulator_disable(priv->vdda); in stm32_adc_core_hw_stop()
603 struct device_node *np = dev->of_node; in stm32_adc_core_switches_probe()
607 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_adc_core_switches_probe()
608 if (IS_ERR(priv->syscfg)) { in stm32_adc_core_switches_probe()
609 ret = PTR_ERR(priv->syscfg); in stm32_adc_core_switches_probe()
610 if (ret != -ENODEV) in stm32_adc_core_switches_probe()
613 priv->syscfg = NULL; in stm32_adc_core_switches_probe()
617 if (priv->cfg->has_syscfg & HAS_VBOOSTER && in stm32_adc_core_switches_probe()
618 of_property_read_bool(np, "booster-supply")) { in stm32_adc_core_switches_probe()
619 priv->booster = devm_regulator_get_optional(dev, "booster"); in stm32_adc_core_switches_probe()
620 if (IS_ERR(priv->booster)) { in stm32_adc_core_switches_probe()
621 ret = PTR_ERR(priv->booster); in stm32_adc_core_switches_probe()
622 if (ret != -ENODEV) in stm32_adc_core_switches_probe()
625 priv->booster = NULL; in stm32_adc_core_switches_probe()
630 if (priv->cfg->has_syscfg & HAS_ANASWVDD && in stm32_adc_core_switches_probe()
631 of_property_read_bool(np, "vdd-supply")) { in stm32_adc_core_switches_probe()
632 priv->vdd = devm_regulator_get_optional(dev, "vdd"); in stm32_adc_core_switches_probe()
633 if (IS_ERR(priv->vdd)) { in stm32_adc_core_switches_probe()
634 ret = PTR_ERR(priv->vdd); in stm32_adc_core_switches_probe()
635 if (ret != -ENODEV) in stm32_adc_core_switches_probe()
638 priv->vdd = NULL; in stm32_adc_core_switches_probe()
642 if (priv->vdd) { in stm32_adc_core_switches_probe()
643 ret = regulator_enable(priv->vdd); in stm32_adc_core_switches_probe()
649 ret = regulator_get_voltage(priv->vdd); in stm32_adc_core_switches_probe()
652 regulator_disable(priv->vdd); in stm32_adc_core_switches_probe()
655 priv->vdd_uv = ret; in stm32_adc_core_switches_probe()
657 regulator_disable(priv->vdd); in stm32_adc_core_switches_probe()
666 struct device_node *np = pdev->dev.of_node; in stm32_adc_probe_identification()
672 if (!priv->cfg->ipid) in stm32_adc_probe_identification()
676 readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR)); in stm32_adc_probe_identification()
677 if (id != priv->cfg->ipid) { in stm32_adc_probe_identification()
678 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id); in stm32_adc_probe_identification()
679 return -EINVAL; in stm32_adc_probe_identification()
686 /* Count child nodes with stm32 adc compatible */ in stm32_adc_probe_identification()
687 if (strstr(compat, "st,stm32") && strstr(compat, "adc")) in stm32_adc_probe_identification()
691 val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0); in stm32_adc_probe_identification()
692 priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val); in stm32_adc_probe_identification()
693 if (count > priv->nb_adc_max) { in stm32_adc_probe_identification()
694 dev_err(&pdev->dev, "Unexpected child number: %d", count); in stm32_adc_probe_identification()
695 return -EINVAL; in stm32_adc_probe_identification()
698 val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR); in stm32_adc_probe_identification()
699 dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n", in stm32_adc_probe_identification()
709 struct device *dev = &pdev->dev; in stm32_adc_probe()
710 struct device_node *np = pdev->dev.of_node; in stm32_adc_probe()
717 if (!pdev->dev.of_node) in stm32_adc_probe()
718 return -ENODEV; in stm32_adc_probe()
720 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in stm32_adc_probe()
722 return -ENOMEM; in stm32_adc_probe()
723 platform_set_drvdata(pdev, &priv->common); in stm32_adc_probe()
725 of_id = of_match_device(dev->driver->of_match_table, dev); in stm32_adc_probe()
727 return -ENODEV; in stm32_adc_probe()
729 priv->cfg = (const struct stm32_adc_priv_cfg *)of_id->data; in stm32_adc_probe()
730 priv->nb_adc_max = priv->cfg->num_adcs; in stm32_adc_probe()
731 spin_lock_init(&priv->common.lock); in stm32_adc_probe()
733 priv->common.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_adc_probe()
734 if (IS_ERR(priv->common.base)) in stm32_adc_probe()
735 return PTR_ERR(priv->common.base); in stm32_adc_probe()
736 priv->common.phys_base = res->start; in stm32_adc_probe()
738 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); in stm32_adc_probe()
739 if (IS_ERR(priv->vdda)) in stm32_adc_probe()
740 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), in stm32_adc_probe()
743 priv->vref = devm_regulator_get(&pdev->dev, "vref"); in stm32_adc_probe()
744 if (IS_ERR(priv->vref)) in stm32_adc_probe()
745 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), in stm32_adc_probe()
746 "vref get failed\n"); in stm32_adc_probe()
748 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); in stm32_adc_probe()
749 if (IS_ERR(priv->aclk)) in stm32_adc_probe()
750 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), in stm32_adc_probe()
751 "Can't get 'adc' clock\n"); in stm32_adc_probe()
753 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); in stm32_adc_probe()
754 if (IS_ERR(priv->bclk)) in stm32_adc_probe()
755 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), in stm32_adc_probe()
776 ret = regulator_get_voltage(priv->vref); in stm32_adc_probe()
778 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); in stm32_adc_probe()
781 priv->common.vref_mv = ret / 1000; in stm32_adc_probe()
782 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); in stm32_adc_probe()
784 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", in stm32_adc_probe()
787 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); in stm32_adc_probe()
789 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; in stm32_adc_probe()
791 ret = priv->cfg->clk_sel(pdev, priv); in stm32_adc_probe()
799 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); in stm32_adc_probe()
801 dev_err(&pdev->dev, "failed to populate DT children\n"); in stm32_adc_probe()
827 pm_runtime_get_sync(&pdev->dev); in stm32_adc_remove()
828 of_platform_depopulate(&pdev->dev); in stm32_adc_remove()
830 stm32_adc_core_hw_stop(&pdev->dev); in stm32_adc_remove()
831 pm_runtime_disable(&pdev->dev); in stm32_adc_remove()
832 pm_runtime_set_suspended(&pdev->dev); in stm32_adc_remove()
833 pm_runtime_put_noidle(&pdev->dev); in stm32_adc_remove()
898 .compatible = "st,stm32f4-adc-core",
901 .compatible = "st,stm32h7-adc-core",
904 .compatible = "st,stm32mp1-adc-core",
907 .compatible = "st,stm32mp13-adc-core",
918 .name = "stm32-adc-core",
926 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
928 MODULE_ALIAS("platform:stm32-adc-core");