Lines Matching refs:MESON_SAR_ADC_REG3

62 #define MESON_SAR_ADC_REG3					0x0c  macro
430 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_set_chan7_mux()
756 	priv->clk_div.reg = base + MESON_SAR_ADC_REG3;  in meson_sar_adc_clk_init()
776 	priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;  in meson_sar_adc_clk_init()
861 		regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);  in meson_sar_adc_init()
878 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
880 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
987 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
1063 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_enable()
1080 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_enable()
1105 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_disable()