Lines Matching +full:refin1 +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
32 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
33 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
34 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
35 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
36 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
37 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
38 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
39 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
40 /* (AD7792)/24-bit (AD7192)) */
41 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
42 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
77 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
78 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
79 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
81 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
96 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
105 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
106 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
108 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
109 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
110 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
111 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
112 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
114 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
115 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
116 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
117 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
119 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
120 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
121 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
122 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
123 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
124 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
125 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
126 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
127 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
128 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
138 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
209 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
219 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
235 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
239 chan->address); in ad7192_write_syscalib()
241 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
242 chan->address); in ad7192_write_syscalib()
277 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
278 st->conf |= AD7192_CONF_CHAN(channel); in ad7192_set_channel()
280 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
288 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
289 st->mode |= AD7192_MODE_SEL(mode); in ad7192_set_mode()
291 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
297 unsigned int mode = st->mode; in ad7192_append_status()
303 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); in ad7192_append_status()
307 st->mode = mode; in ad7192_append_status()
315 u32 conf = st->conf; in ad7192_disable_all()
320 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_disable_all()
324 st->conf = conf; in ad7192_disable_all()
355 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
367 struct device *dev = &st->sd.spi->dev; in ad7192_clock_select()
373 if (!st->mclk) { in ad7192_clock_select()
374 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) in ad7192_clock_select()
377 if (device_property_read_bool(dev, "adi,clock-xtal")) in ad7192_clock_select()
395 ret = ad_sd_reset(&st->sd, 48); in ad7192_setup()
401 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
407 if (id != st->chip_info->chip_id) in ad7192_setup()
409 id, st->chip_info->chip_id); in ad7192_setup()
411 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | in ad7192_setup()
412 AD7192_MODE_CLKSRC(st->clock_sel) | in ad7192_setup()
415 st->conf = AD7192_CONF_GAIN(0); in ad7192_setup()
417 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable"); in ad7192_setup()
419 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
421 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable"); in ad7192_setup()
422 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
423 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
425 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
426 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_setup()
428 buf_en = device_property_read_bool(dev, "adi,buffer-enable"); in ad7192_setup()
430 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
434 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
437 "adi,burnout-currents-enable"); in ad7192_setup()
439 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
445 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
449 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
458 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
459 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
460 >> (indio_dev->channels[0].scan_type.realbits - in ad7192_setup()
461 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); in ad7192_setup()
464 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
465 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
478 return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX)); in ad7192_show_ac_excitation()
488 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); in ad7192_show_bridge_switch()
510 switch ((u32)this_attr->address) { in ad7192_set()
513 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
515 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
517 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
521 st->conf |= AD7192_CONF_ACX; in ad7192_set()
523 st->conf &= ~AD7192_CONF_ACX; in ad7192_set()
525 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set()
528 ret = -EINVAL; in ad7192_set()
542 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
543 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
546 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_available_filter_freq()
547 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
550 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); in ad7192_get_available_filter_freq()
570 buf[len - 1] = '\n'; in ad7192_show_filter_avail()
625 diff_new = abs(freq - freq_avail[i]); in ad7192_set_3db_filter_freq()
634 st->f_order = AD7192_SYNC4_FILTER; in ad7192_set_3db_filter_freq()
635 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
637 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
640 st->f_order = AD7192_SYNC3_FILTER; in ad7192_set_3db_filter_freq()
641 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
643 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
646 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_set_3db_filter_freq()
647 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
649 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
652 st->f_order = AD7192_NO_SYNC_FILTER; in ad7192_set_3db_filter_freq()
653 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
655 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
659 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
663 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
670 fadc = DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_3db_filter_freq()
671 st->f_order * AD7192_MODE_RATE(st->mode)); in ad7192_get_3db_filter_freq()
673 if (st->conf & AD7192_CONF_CHOP) in ad7192_get_3db_filter_freq()
675 if (st->mode & AD7192_MODE_SINC3) in ad7192_get_3db_filter_freq()
688 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); in ad7192_read_raw()
694 switch (chan->type) { in ad7192_read_raw()
696 mutex_lock(&st->lock); in ad7192_read_raw()
697 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; in ad7192_read_raw()
698 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; in ad7192_read_raw()
699 mutex_unlock(&st->lock); in ad7192_read_raw()
706 return -EINVAL; in ad7192_read_raw()
710 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
714 if (chan->type == IIO_TEMP) in ad7192_read_raw()
715 *val -= 273 * ad7192_get_temp_scale(unipolar); in ad7192_read_raw()
718 *val = st->fclk / in ad7192_read_raw()
719 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); in ad7192_read_raw()
727 return -EINVAL; in ad7192_read_raw()
746 ret = -EINVAL; in ad7192_write_raw()
747 mutex_lock(&st->lock); in ad7192_write_raw()
748 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in ad7192_write_raw()
749 if (val2 == st->scale_avail[i][1]) { in ad7192_write_raw()
751 tmp = st->conf; in ad7192_write_raw()
752 st->conf &= ~AD7192_CONF_GAIN(-1); in ad7192_write_raw()
753 st->conf |= AD7192_CONF_GAIN(i); in ad7192_write_raw()
754 if (tmp == st->conf) in ad7192_write_raw()
756 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, in ad7192_write_raw()
757 3, st->conf); in ad7192_write_raw()
761 mutex_unlock(&st->lock); in ad7192_write_raw()
765 ret = -EINVAL; in ad7192_write_raw()
769 div = st->fclk / (val * st->f_order * 1024); in ad7192_write_raw()
771 ret = -EINVAL; in ad7192_write_raw()
775 st->mode &= ~AD7192_MODE_RATE(-1); in ad7192_write_raw()
776 st->mode |= AD7192_MODE_RATE(div); in ad7192_write_raw()
777 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_write_raw()
783 ret = -EINVAL; in ad7192_write_raw()
803 return -EINVAL; in ad7192_write_raw_get_fmt()
816 *vals = (int *)st->scale_avail; in ad7192_read_avail()
819 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
824 return -EINVAL; in ad7192_read_avail()
830 u32 conf = st->conf; in ad7192_update_scan_mode()
838 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_update_scan_mode()
842 st->conf = conf; in ad7192_update_scan_mode()
871 .differential = ((_channel2) == -1 ? 0 : 1), \
899 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
903 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
958 switch (st->chip_info->chip_id) { in ad7192_channels_config()
960 indio_dev->channels = ad7193_channels; in ad7192_channels_config()
961 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); in ad7192_channels_config()
964 indio_dev->channels = ad7192_channels; in ad7192_channels_config()
965 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); in ad7192_channels_config()
983 if (!spi->irq) { in ad7192_probe()
984 dev_err(&spi->dev, "no IRQ?\n"); in ad7192_probe()
985 return -ENODEV; in ad7192_probe()
988 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in ad7192_probe()
990 return -ENOMEM; in ad7192_probe()
994 mutex_init(&st->lock); in ad7192_probe()
996 st->avdd = devm_regulator_get(&spi->dev, "avdd"); in ad7192_probe()
997 if (IS_ERR(st->avdd)) in ad7192_probe()
998 return PTR_ERR(st->avdd); in ad7192_probe()
1000 ret = regulator_enable(st->avdd); in ad7192_probe()
1002 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); in ad7192_probe()
1006 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); in ad7192_probe()
1010 ret = devm_regulator_get_enable(&spi->dev, "dvdd"); in ad7192_probe()
1012 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n"); in ad7192_probe()
1014 st->vref = devm_regulator_get_optional(&spi->dev, "vref"); in ad7192_probe()
1015 if (IS_ERR(st->vref)) { in ad7192_probe()
1016 if (PTR_ERR(st->vref) != -ENODEV) in ad7192_probe()
1017 return PTR_ERR(st->vref); in ad7192_probe()
1019 ret = regulator_get_voltage(st->avdd); in ad7192_probe()
1021 return dev_err_probe(&spi->dev, ret, in ad7192_probe()
1024 ret = regulator_enable(st->vref); in ad7192_probe()
1026 dev_err(&spi->dev, "Failed to enable specified Vref supply\n"); in ad7192_probe()
1030 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref); in ad7192_probe()
1034 ret = regulator_get_voltage(st->vref); in ad7192_probe()
1036 return dev_err_probe(&spi->dev, ret, in ad7192_probe()
1039 st->int_vref_mv = ret / 1000; in ad7192_probe()
1041 st->chip_info = spi_get_device_match_data(spi); in ad7192_probe()
1042 if (!st->chip_info) in ad7192_probe()
1043 return -ENODEV; in ad7192_probe()
1045 indio_dev->name = st->chip_info->name; in ad7192_probe()
1046 indio_dev->modes = INDIO_DIRECT_MODE; in ad7192_probe()
1052 if (st->chip_info->chip_id == CHIPID_AD7195) in ad7192_probe()
1053 indio_dev->info = &ad7195_info; in ad7192_probe()
1055 indio_dev->info = &ad7192_info; in ad7192_probe()
1057 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); in ad7192_probe()
1061 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); in ad7192_probe()
1065 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_probe()
1067 st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk"); in ad7192_probe()
1068 if (IS_ERR(st->mclk)) in ad7192_probe()
1069 return PTR_ERR(st->mclk); in ad7192_probe()
1071 st->clock_sel = ad7192_clock_select(st); in ad7192_probe()
1073 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || in ad7192_probe()
1074 st->clock_sel == AD7192_CLK_EXT_MCLK2) { in ad7192_probe()
1075 st->fclk = clk_get_rate(st->mclk); in ad7192_probe()
1076 if (!ad7192_valid_external_frequency(st->fclk)) { in ad7192_probe()
1077 dev_err(&spi->dev, in ad7192_probe()
1079 return -EINVAL; in ad7192_probe()
1083 ret = ad7192_setup(indio_dev, &spi->dev); in ad7192_probe()
1087 return devm_iio_device_register(&spi->dev, indio_dev); in ad7192_probe()