iio/adc/ad7124.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * AD7124 SPI ADC driver
26 /* AD7124 registers */
44 #define AD7124_STATUS_POR_FLAG_MSK	BIT(4)
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK		GENMASK(7, 4)
72 #define AD7124_CHANNEL_AINM_MSK	GENMASK(4, 0)
78 #define AD7124_CONFIG_REF_SEL_MSK	GENMASK(4, 3)
117 	1, 2, 4, 8, 16, 32, 64, 128
175 	struct regulator *vref[4];
203 		.name = "ad7124-4",
208 		.name = "ad7124-8",
224 		diff_new = abs(val - array[i]);
243 	ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
250 	return ad_sd_write_reg(&st->sd, addr, bytes, readval);
258 	st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
259 	st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
261 	return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
268 	fclk = clk_get_rate(st->mclk);
282 	if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
283 		st->channels[channel].cfg.live = false;
286 	st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
287 	st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
295 	fadc = st->channels[channel].cfg.odr;
297 	switch (st->channels[channel].cfg.filter_type) {
303 		return -EINVAL;
326 	if (new_odr != st->channels[channel].cfg.odr)
327 		st->channels[channel].cfg.live = false;
329 	st->channels[channel].cfg.filter_type = new_filter;
330 	st->channels[channel].cfg.odr = new_odr;
341 	for (i = 0; i < st->num_channels; i++) {
342 		cfg_aux = &st->channels[i].cfg;
344 		if (cfg_aux->live &&
345 		    !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
356 	free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
358 		return -1;
365 	unsigned int refsel = cfg->refsel;
371 		if (IS_ERR(st->vref[refsel])) {
372 			dev_err(&st->sd.spi->dev,
375 			return PTR_ERR(st->vref[refsel]);
377 		cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
379 		cfg->vref_mv /= 1000;
382 		cfg->vref_mv = 2500;
383 		st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
384 		st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
385 		return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
386 				      2, st->adc_control);
388 		dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
389 		return -EINVAL;
400 	cfg->cfg_slot = cfg_slot;
402 	tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
403 	val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
405 	ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
409 	tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
410 	ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
415 	ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
416 				    AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
420 	return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
421 				     AD7124_CONFIG_PGA(cfg->pga_bits), 2);
435 	ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
439 	lru_cfg->live = false;
442 	assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
445 	for (i = 0; i < st->num_channels; i++) {
446 		cfg = &st->channels[i].cfg;
448 		if (cfg->cfg_slot == lru_cfg->cfg_slot)
449 			cfg->live = false;
463 		kfifo_put(&st->live_cfgs_fifo, cfg);
468 			return -EINVAL;
471 		free_cfg_slot = lru_cfg->cfg_slot;
472 		kfifo_put(&st->live_cfgs_fifo, cfg);
476 	assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
483 	ch->cfg.live = true;
484 	return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
485 			      AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
490 	struct ad7124_channel_config *cfg = &st->channels[address].cfg;
497 	if (!cfg->live) {
503 			cfg->cfg_slot = live_cfg->cfg_slot;
507 	return ad7124_enable_channel(st, &st->channels[address]);
522 	mutex_lock(&st->cfgs_lock);
524 	mutex_unlock(&st->cfgs_lock);
532 	unsigned int adc_control = st->adc_control;
538 	ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
542 	st->adc_control = adc_control;
553 	for (i = 0; i < st->num_channels; i++) {
590 		ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
591 				      st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
597 		mutex_lock(&st->cfgs_lock);
599 		idx = st->channels[chan->address].cfg.pga_bits;
600 		*val = st->channels[chan->address].cfg.vref_mv;
601 		if (st->channels[chan->address].cfg.bipolar)
602 			*val2 = chan->scan_type.realbits - 1 + idx;
604 			*val2 = chan->scan_type.realbits + idx;
606 		mutex_unlock(&st->cfgs_lock);
609 		mutex_lock(&st->cfgs_lock);
610 		if (st->channels[chan->address].cfg.bipolar)
611 			*val = -(1 << (chan->scan_type.realbits - 1));
615 		mutex_unlock(&st->cfgs_lock);
618 		mutex_lock(&st->cfgs_lock);
619 		*val = st->channels[chan->address].cfg.odr;
620 		mutex_unlock(&st->cfgs_lock);
624 		mutex_lock(&st->cfgs_lock);
625 		*val = ad7124_get_3db_filter_freq(st, chan->scan_index);
626 		mutex_unlock(&st->cfgs_lock);
630 		return -EINVAL;
642 	mutex_lock(&st->cfgs_lock);
647 			ret = -EINVAL;
651 		ad7124_set_channel_odr(st, chan->address, val);
655 			ret = -EINVAL;
659 		if (st->channels[chan->address].cfg.bipolar)
660 			full_scale = 1 << (chan->scan_type.realbits - 1);
662 			full_scale = 1 << chan->scan_type.realbits;
664 		vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
669 		if (st->channels[chan->address].cfg.pga_bits != res)
670 			st->channels[chan->address].cfg.live = false;
672 		st->channels[chan->address].cfg.pga_bits = res;
676 			ret = -EINVAL;
680 		ad7124_set_3db_filter_freq(st, chan->address, val);
683 		ret =  -EINVAL;
686 	mutex_unlock(&st->cfgs_lock);
699 		return -EINVAL;
702 		ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
705 		ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
731 	mutex_lock(&st->cfgs_lock);
732 	for (i = 0; i < st->num_channels; i++) {
735 			ret = __ad7124_set_channel(&st->sd, i);
740 			mutex_unlock(&st->cfgs_lock);
746 	mutex_unlock(&st->cfgs_lock);
765 	ret = ad_sd_reset(&st->sd, 64);
772 		ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
779 		/* The AD7124 requires typically 2ms to power up and settle */
781 	} while (--timeout);
783 	dev_err(&st->sd.spi->dev, "Soft reset failed\n");
785 	return -EIO;
793 	ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
800 	if (chip_id != st->chip_info->chip_id) {
801 		dev_err(&st->sd.spi->dev,
803 			st->chip_info->chip_id, chip_id);
804 		return -ENODEV;
808 		dev_err(&st->sd.spi->dev,
810 		return -ENODEV;
826 	st->num_channels = device_get_child_node_count(dev);
827 	if (!st->num_channels)
828 		return dev_err_probe(dev, -ENODEV, "no channel children\n");
830 	chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
833 		return -ENOMEM;
835 	channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
838 		return -ENOMEM;
840 	indio_dev->channels = chan;
841 	indio_dev->num_channels = st->num_channels;
842 	st->channels = channels;
849 		if (channel >= indio_dev->num_channels)
850 			return dev_err_probe(dev, -EINVAL,
853 		ret = fwnode_property_read_u32_array(child, "diff-channels",
858 		st->channels[channel].nr = channel;
859 		st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
862 		cfg = &st->channels[channel].cfg;
863 		cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
865 		ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
867 			cfg->refsel = AD7124_INT_REF;
869 			cfg->refsel = tmp;
871 		cfg->buf_positive =
872 			fwnode_property_read_bool(child, "adi,buffered-positive");
873 		cfg->buf_negative =
874 			fwnode_property_read_bool(child, "adi,buffered-negative");
891 	fclk = clk_get_rate(st->mclk);
893 		return -EINVAL;
900 		ret = clk_set_rate(st->mclk, fclk);
906 	st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
907 	st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
908 	ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
912 	mutex_init(&st->cfgs_lock);
913 	INIT_KFIFO(st->live_cfgs_fifo);
914 	for (i = 0; i < st->num_channels; i++) {
916 		ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
928 		ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, 0);
948 		return -ENODEV;
950 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
952 		return -ENOMEM;
956 	st->chip_info = info;
958 	indio_dev->name = st->chip_info->name;
959 	indio_dev->modes = INDIO_DIRECT_MODE;
960 	indio_dev->info = &ad7124_info;
962 	ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
966 	ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
970 	for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
974 		st->vref[i] = devm_regulator_get_optional(&spi->dev,
976 		if (PTR_ERR(st->vref[i]) == -ENODEV)
978 		else if (IS_ERR(st->vref[i]))
979 			return PTR_ERR(st->vref[i]);
981 		ret = regulator_enable(st->vref[i]);
985 		ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
986 					       st->vref[i]);
991 	st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
992 	if (IS_ERR(st->mclk))
993 		return PTR_ERR(st->mclk);
1007 	ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1011 	return devm_iio_device_register(&spi->dev, indio_dev);
1016 	{ .compatible = "adi,ad7124-4",
1018 	{ .compatible = "adi,ad7124-8",
1025 	{ "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1026 	{ "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1033 		.name = "ad7124",
1042 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");