271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)  in adxl367_set_measure_en()  argument
277 	ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,  in adxl367_set_measure_en()
294 static void adxl367_scale_act_thresholds(struct adxl367_state *st,  in adxl367_scale_act_thresholds()  argument
298 	st->act_threshold = st->act_threshold  in adxl367_scale_act_thresholds()
301 	st->inact_threshold = st->inact_threshold  in adxl367_scale_act_thresholds()
306 static int _adxl367_set_act_threshold(struct adxl367_state *st,  in _adxl367_set_act_threshold()  argument
316 	st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,  in _adxl367_set_act_threshold()
319 	st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,  in _adxl367_set_act_threshold()
323 	ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,  in _adxl367_set_act_threshold()
324 				sizeof(st->act_threshold_buf));  in _adxl367_set_act_threshold()
329 		st->act_threshold = threshold;  in _adxl367_set_act_threshold()
331 		st->inact_threshold = threshold;  in _adxl367_set_act_threshold()
336 static int adxl367_set_act_threshold(struct adxl367_state *st,  in adxl367_set_act_threshold()  argument
342 	mutex_lock(&st->lock);  in adxl367_set_act_threshold()
344 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_act_threshold()
348 	ret = _adxl367_set_act_threshold(st, act, threshold);  in adxl367_set_act_threshold()
352 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_act_threshold()
355 	mutex_unlock(&st->lock);  in adxl367_set_act_threshold()
360 static int adxl367_set_act_proc_mode(struct adxl367_state *st,  in adxl367_set_act_proc_mode()  argument
363 	return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,  in adxl367_set_act_proc_mode()
369 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,  in adxl367_set_act_interrupt_en()  argument
375 	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,  in adxl367_set_act_interrupt_en()
379 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,  in adxl367_get_act_interrupt_en()  argument
387 	ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);  in adxl367_get_act_interrupt_en()
396 static int adxl367_set_act_en(struct adxl367_state *st,  in adxl367_set_act_en()  argument
402 	return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,  in adxl367_set_act_en()
407 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,  in adxl367_set_fifo_watermark_interrupt_en()  argument
410 	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,  in adxl367_set_fifo_watermark_interrupt_en()
415 static int adxl367_get_fifo_mode(struct adxl367_state *st,  in adxl367_get_fifo_mode()  argument
421 	ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);  in adxl367_get_fifo_mode()
430 static int adxl367_set_fifo_mode(struct adxl367_state *st,  in adxl367_set_fifo_mode()  argument
433 	return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_mode()
439 static int adxl367_set_fifo_format(struct adxl367_state *st,  in adxl367_set_fifo_format()  argument
442 	return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_format()
448 static int adxl367_set_fifo_watermark(struct adxl367_state *st,  in adxl367_set_fifo_watermark()  argument
451 	unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;  in adxl367_set_fifo_watermark()
458 	fifo_samples /= st->fifo_set_size;  in adxl367_set_fifo_watermark()
467 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_watermark()
472 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,  in adxl367_set_fifo_watermark()
477 	st->fifo_watermark = fifo_watermark;  in adxl367_set_fifo_watermark()
485 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_set_range()  local
492 	mutex_lock(&st->lock);  in adxl367_set_range()
494 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_range()
498 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,  in adxl367_set_range()
505 	adxl367_scale_act_thresholds(st, st->range, range);  in adxl367_set_range()
508 	ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,  in adxl367_set_range()
509 					 st->act_threshold);  in adxl367_set_range()
513 	ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,  in adxl367_set_range()
514 					 st->inact_threshold);  in adxl367_set_range()
518 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_range()
522 	st->range = range;  in adxl367_set_range()
525 	mutex_unlock(&st->lock);  in adxl367_set_range()
532 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)  in adxl367_time_ms_to_samples()  argument
534 	int freq_hz = adxl367_samp_freq_tbl[st->odr][0];  in adxl367_time_ms_to_samples()
535 	int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];  in adxl367_time_ms_to_samples()
542 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)  in _adxl367_set_act_time_ms()  argument
544 	unsigned int val = adxl367_time_ms_to_samples(st, ms);  in _adxl367_set_act_time_ms()
550 	ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);  in _adxl367_set_act_time_ms()
554 	st->act_time_ms = ms;  in _adxl367_set_act_time_ms()
559 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)  in _adxl367_set_inact_time_ms()  argument
561 	unsigned int val = adxl367_time_ms_to_samples(st, ms);  in _adxl367_set_inact_time_ms()
567 	st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,  in _adxl367_set_inact_time_ms()
570 	st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,  in _adxl367_set_inact_time_ms()
574 	ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,  in _adxl367_set_inact_time_ms()
575 				st->inact_time_buf, sizeof(st->inact_time_buf));  in _adxl367_set_inact_time_ms()
579 	st->inact_time_ms = ms;  in _adxl367_set_inact_time_ms()
584 static int adxl367_set_act_time_ms(struct adxl367_state *st,  in adxl367_set_act_time_ms()  argument
590 	mutex_lock(&st->lock);  in adxl367_set_act_time_ms()
592 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_act_time_ms()
597 		ret = _adxl367_set_act_time_ms(st, ms);  in adxl367_set_act_time_ms()
599 		ret = _adxl367_set_inact_time_ms(st, ms);  in adxl367_set_act_time_ms()
604 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_act_time_ms()
607 	mutex_unlock(&st->lock);  in adxl367_set_act_time_ms()
612 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)  in _adxl367_set_odr()  argument
616 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,  in _adxl367_set_odr()
624 	ret = _adxl367_set_act_time_ms(st, st->act_time_ms);  in _adxl367_set_odr()
628 	ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms);  in _adxl367_set_odr()
632 	st->odr = odr;  in _adxl367_set_odr()
639 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_set_odr()  local
646 	mutex_lock(&st->lock);  in adxl367_set_odr()
648 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_odr()
652 	ret = _adxl367_set_odr(st, odr);  in adxl367_set_odr()
656 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_odr()
659 	mutex_unlock(&st->lock);  in adxl367_set_odr()
666 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,  in adxl367_set_temp_adc_en()  argument
669 	return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,  in adxl367_set_temp_adc_en()
673 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,  in adxl367_set_temp_adc_reg_en()  argument
680 		ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);  in adxl367_set_temp_adc_reg_en()
683 		ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);  in adxl367_set_temp_adc_reg_en()
698 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,  in adxl367_set_temp_adc_mask_en()  argument
703 		return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);  in adxl367_set_temp_adc_mask_en()
705 		return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);  in adxl367_set_temp_adc_mask_en()
710 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,  in adxl367_find_odr()  argument
729 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,  in adxl367_find_range()  argument
752 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_sample()  local
760 	mutex_lock(&st->lock);  in adxl367_read_sample()
762 	ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);  in adxl367_read_sample()
766 	ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,  in adxl367_read_sample()
767 			       sizeof(st->sample_buf));  in adxl367_read_sample()
771 	sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));  in adxl367_read_sample()
774 	ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);  in adxl367_read_sample()
777 	mutex_unlock(&st->lock);  in adxl367_read_sample()
784 static int adxl367_get_status(struct adxl367_state *st, u8 *status,  in adxl367_get_status()  argument
790 	ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,  in adxl367_get_status()
791 			       st->status_buf, sizeof(st->status_buf));  in adxl367_get_status()
795 	st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;  in adxl367_get_status()
797 	*status = st->status_buf[0];  in adxl367_get_status()
798 	*fifo_entries = get_unaligned_le16(&st->status_buf[1]);  in adxl367_get_status()
825 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_push_fifo_data()  local
832 	fifo_entries -= fifo_entries % st->fifo_set_size;  in adxl367_push_fifo_data()
834 	ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);  in adxl367_push_fifo_data()
836 		dev_err(st->dev, "Failed to read FIFO: %d\n", ret);  in adxl367_push_fifo_data()
840 	for (i = 0; i < fifo_entries; i += st->fifo_set_size)  in adxl367_push_fifo_data()
841 		iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);  in adxl367_push_fifo_data()
849 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_irq_handler()  local
855 	ret = adxl367_get_status(st, &status, &fifo_entries);  in adxl367_irq_handler()
870 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_reg_access()  local
873 		return regmap_read(st->regmap, reg, readval);  in adxl367_reg_access()
875 		return regmap_write(st->regmap, reg, writeval);  in adxl367_reg_access()
882 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_raw()  local
890 			mutex_lock(&st->lock);  in adxl367_read_raw()
891 			*val = adxl367_range_scale_tbl[st->range][0];  in adxl367_read_raw()
892 			*val2 = adxl367_range_scale_tbl[st->range][1];  in adxl367_read_raw()
893 			mutex_unlock(&st->lock);  in adxl367_read_raw()
918 		mutex_lock(&st->lock);  in adxl367_read_raw()
919 		*val = adxl367_samp_freq_tbl[st->odr][0];  in adxl367_read_raw()
920 		*val2 = adxl367_samp_freq_tbl[st->odr][1];  in adxl367_read_raw()
921 		mutex_unlock(&st->lock);  in adxl367_read_raw()
932 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_raw()  local
939 		ret = adxl367_find_odr(st, val, val2, &odr);  in adxl367_write_raw()
948 		ret = adxl367_find_range(st, val, val2, &range);  in adxl367_write_raw()
1005 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_event_value()  local
1011 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1012 			*val = st->act_threshold;  in adxl367_read_event_value()
1013 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1016 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1017 			*val = st->inact_threshold;  in adxl367_read_event_value()
1018 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1027 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1028 			*val = st->act_time_ms;  in adxl367_read_event_value()
1029 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1033 			mutex_lock(&st->lock);  in adxl367_read_event_value()
1034 			*val = st->inact_time_ms;  in adxl367_read_event_value()
1035 			mutex_unlock(&st->lock);  in adxl367_read_event_value()
1053 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_event_value()  local
1062 			return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);  in adxl367_write_event_value()
1064 			return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);  in adxl367_write_event_value()
1075 			return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);  in adxl367_write_event_value()
1077 			return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);  in adxl367_write_event_value()
1091 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_event_config()  local
1097 		ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);  in adxl367_read_event_config()
1100 		ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);  in adxl367_read_event_config()
1113 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_event_config()  local
1132 	mutex_lock(&st->lock);  in adxl367_write_event_config()
1134 	ret = adxl367_set_measure_en(st, false);  in adxl367_write_event_config()
1138 	ret = adxl367_set_act_interrupt_en(st, act, state);  in adxl367_write_event_config()
1142 	ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED  in adxl367_write_event_config()
1147 	ret = adxl367_set_measure_en(st, true);  in adxl367_write_event_config()
1150 	mutex_unlock(&st->lock);  in adxl367_write_event_config()
1161 	struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));  in adxl367_get_fifo_enabled()  local
1165 	ret = adxl367_get_fifo_mode(st, &fifo_mode);  in adxl367_get_fifo_enabled()
1176 	struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));  in adxl367_get_fifo_watermark()  local
1179 	mutex_lock(&st->lock);  in adxl367_get_fifo_watermark()
1180 	fifo_watermark = st->fifo_watermark;  in adxl367_get_fifo_watermark()
1181 	mutex_unlock(&st->lock);  in adxl367_get_fifo_watermark()
1204 	struct adxl367_state *st  = iio_priv(indio_dev);  in adxl367_set_watermark()  local
1210 	mutex_lock(&st->lock);  in adxl367_set_watermark()
1212 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_watermark()
1216 	ret = adxl367_set_fifo_watermark(st, val);  in adxl367_set_watermark()
1220 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_watermark()
1223 	mutex_unlock(&st->lock);  in adxl367_set_watermark()
1249 	struct adxl367_state *st  = iio_priv(indio_dev);  in adxl367_update_scan_mode()  local
1256 	mutex_lock(&st->lock);  in adxl367_update_scan_mode()
1258 	ret = adxl367_set_measure_en(st, false);  in adxl367_update_scan_mode()
1262 	ret = adxl367_set_fifo_format(st, fifo_format);  in adxl367_update_scan_mode()
1266 	ret = adxl367_set_measure_en(st, true);  in adxl367_update_scan_mode()
1270 	st->fifo_set_size = bitmap_weight(active_scan_mask,  in adxl367_update_scan_mode()
1274 	mutex_unlock(&st->lock);  in adxl367_update_scan_mode()
1281 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_buffer_postenable()  local
1284 	mutex_lock(&st->lock);  in adxl367_buffer_postenable()
1286 	ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,  in adxl367_buffer_postenable()
1291 	ret = adxl367_set_measure_en(st, false);  in adxl367_buffer_postenable()
1295 	ret = adxl367_set_fifo_watermark_interrupt_en(st, true);  in adxl367_buffer_postenable()
1299 	ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);  in adxl367_buffer_postenable()
1303 	ret = adxl367_set_measure_en(st, true);  in adxl367_buffer_postenable()
1306 	mutex_unlock(&st->lock);  in adxl367_buffer_postenable()
1313 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_buffer_predisable()  local
1316 	mutex_lock(&st->lock);  in adxl367_buffer_predisable()
1318 	ret = adxl367_set_measure_en(st, false);  in adxl367_buffer_predisable()
1322 	ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);  in adxl367_buffer_predisable()
1326 	ret = adxl367_set_fifo_watermark_interrupt_en(st, false);  in adxl367_buffer_predisable()
1330 	ret = adxl367_set_measure_en(st, true);  in adxl367_buffer_predisable()
1334 	ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,  in adxl367_buffer_predisable()
1338 	mutex_unlock(&st->lock);  in adxl367_buffer_predisable()
1427 static int adxl367_verify_devid(struct adxl367_state *st)  in adxl367_verify_devid()  argument
1432 	ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val);  in adxl367_verify_devid()
1434 		return dev_err_probe(st->dev, ret, "Failed to read dev id\n");  in adxl367_verify_devid()
1437 		return dev_err_probe(st->dev, -ENODEV,  in adxl367_verify_devid()
1444 static int adxl367_setup(struct adxl367_state *st)  in adxl367_setup()  argument
1448 	ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,  in adxl367_setup()
1453 	ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,  in adxl367_setup()
1458 	ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);  in adxl367_setup()
1462 	ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);  in adxl367_setup()
1466 	ret = _adxl367_set_act_time_ms(st, 10);  in adxl367_setup()
1470 	ret = _adxl367_set_inact_time_ms(st, 10000);  in adxl367_setup()
1474 	return adxl367_set_measure_en(st, true);  in adxl367_setup()
1482 	struct adxl367_state *st;  in adxl367_probe()  local
1485 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));  in adxl367_probe()
1489 	st = iio_priv(indio_dev);  in adxl367_probe()
1490 	st->dev = dev;  in adxl367_probe()
1491 	st->regmap = regmap;  in adxl367_probe()
1492 	st->context = context;  in adxl367_probe()
1493 	st->ops = ops;  in adxl367_probe()
1495 	mutex_init(&st->lock);  in adxl367_probe()
1504 	ret = devm_regulator_bulk_get_enable(st->dev,  in adxl367_probe()
1508 		return dev_err_probe(st->dev, ret,  in adxl367_probe()
1511 	ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);  in adxl367_probe()
1517 	ret = adxl367_verify_devid(st);  in adxl367_probe()
1521 	ret = adxl367_setup(st);  in adxl367_probe()
1525 	ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,  in adxl367_probe()
1531 	ret = devm_request_threaded_irq(st->dev, irq, NULL,  in adxl367_probe()
1535 		return dev_err_probe(st->dev, ret, "Failed to request irq\n");  in adxl367_probe()