Lines Matching refs:pio_reg_write
24 #define pio_reg_write(r, v) writel(v, hci->PIO_regs + (PIO_##r)) macro
183 pio_reg_write(DATA_BUFFER_THLD_CTRL, val); in hci_pio_init()
196 pio_reg_write(QUEUE_THLD_CTRL, val); in hci_pio_init()
200 pio_reg_write(INTR_SIGNAL_ENABLE, 0x0); in hci_pio_init()
201 pio_reg_write(INTR_STATUS_ENABLE, 0xffffffff); in hci_pio_init()
213 pio_reg_write(INTR_SIGNAL_ENABLE, 0x0); in hci_pio_cleanup()
231 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[0]); in hci_pio_write_cmd()
232 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[1]); in hci_pio_write_cmd()
236 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[2]); in hci_pio_write_cmd()
237 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[3]); in hci_pio_write_cmd()
326 pio_reg_write(XFER_DATA_PORT, *p++); in hci_pio_do_tx()
340 pio_reg_write(XFER_DATA_PORT, *p); in hci_pio_do_tx()
613 pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs); in hci_pio_queue_xfer()
750 pio_reg_write(QUEUE_THLD_CTRL, regval); in hci_pio_set_ibi_thresh()
1010 pio_reg_write(INTR_STATUS, status & STAT_LATENCY_WARNINGS); in hci_pio_irq_handler()
1017 pio_reg_write(INTR_STATUS, status & STAT_ALL_ERRORS); in hci_pio_irq_handler()
1025 pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs); in hci_pio_irq_handler()