Lines Matching refs:rh_reg_write
56 #define rh_reg_write(r, v) writel(v, rh->regs + (RH_##r)) macro
177 rh_reg_write(INTR_SIGNAL_ENABLE, 0); in hci_dma_cleanup()
178 rh_reg_write(RING_CONTROL, 0); in hci_dma_cleanup()
179 rh_reg_write(CR_SETUP, 0); in hci_dma_cleanup()
180 rh_reg_write(IBI_SETUP, 0); in hci_dma_cleanup()
265 rh_reg_write(CMD_RING_BASE_LO, lo32(rh->xfer_dma)); in hci_dma_init()
266 rh_reg_write(CMD_RING_BASE_HI, hi32(rh->xfer_dma)); in hci_dma_init()
267 rh_reg_write(RESP_RING_BASE_LO, lo32(rh->resp_dma)); in hci_dma_init()
268 rh_reg_write(RESP_RING_BASE_HI, hi32(rh->resp_dma)); in hci_dma_init()
271 rh_reg_write(CR_SETUP, regval); in hci_dma_init()
273 rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff); in hci_dma_init()
274 rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY | in hci_dma_init()
324 rh_reg_write(IBI_SETUP, regval); in hci_dma_init()
328 rh_reg_write(INTR_SIGNAL_ENABLE, regval); in hci_dma_init()
331 rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); in hci_dma_init()
438 rh_reg_write(RING_OPERATION1, op1_val); in hci_dma_queue_xfer()
453 rh_reg_write(RING_CONTROL, RING_CTRL_ABORT); in hci_dma_dequeue_xfer()
494 rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); in hci_dma_dequeue_xfer()
541 rh_reg_write(RING_OPERATION1, op1_val); in hci_dma_xfer_done()
724 rh_reg_write(RING_OPERATION1, op1_val); in hci_dma_process_ibi()
732 rh_reg_write(CHUNK_CONTROL, rh_reg_read(CHUNK_CONTROL) + ibi_chunks); in hci_dma_process_ibi()
754 rh_reg_write(INTR_STATUS, status); in hci_dma_irq_handler()