master/mipi-i3c-hci/cmd_v2.c

24 #define CMD_0_ATTR_U			FIELD_PREP(CMD_0_ATTR, 0x4)
26 #define CMD_U3_HDR_TSP_ML_CTRL(v)	FIELD_PREP(W3_MASK(107, 104), v)
27 #define CMD_U3_IDB4(v)			FIELD_PREP(W3_MASK(103,  96), v)
28 #define CMD_U3_HDR_CMD(v)		FIELD_PREP(W3_MASK(103,  96), v)
29 #define CMD_U2_IDB3(v)			FIELD_PREP(W2_MASK( 95,  88), v)
30 #define CMD_U2_HDR_BT(v)		FIELD_PREP(W2_MASK( 95,  88), v)
31 #define CMD_U2_IDB2(v)			FIELD_PREP(W2_MASK( 87,  80), v)
32 #define CMD_U2_BT_CMD2(v)		FIELD_PREP(W2_MASK( 87,  80), v)
33 #define CMD_U2_IDB1(v)			FIELD_PREP(W2_MASK( 79,  72), v)
34 #define CMD_U2_BT_CMD1(v)		FIELD_PREP(W2_MASK( 79,  72), v)
35 #define CMD_U2_IDB0(v)			FIELD_PREP(W2_MASK( 71,  64), v)
36 #define CMD_U2_BT_CMD0(v)		FIELD_PREP(W2_MASK( 71,  64), v)
37 #define CMD_U1_ERR_HANDLING(v)		FIELD_PREP(W1_MASK( 63,  62), v)
38 #define CMD_U1_ADD_FUNC(v)		FIELD_PREP(W1_MASK( 61,  56), v)
40 #define CMD_U1_DATA_LENGTH(v)		FIELD_PREP(W1_MASK( 53,  32), v)
44 #define CMD_U0_NACK_RCNT(v)		FIELD_PREP(W0_MASK( 28,  27), v)
45 #define CMD_U0_IDB_COUNT(v)		FIELD_PREP(W0_MASK( 26,  24), v)
46 #define CMD_U0_MODE_INDEX(v)		FIELD_PREP(W0_MASK( 22,  18), v)
47 #define CMD_U0_XFER_RATE(v)		FIELD_PREP(W0_MASK( 17,  15), v)
48 #define CMD_U0_DEV_ADDRESS(v)		FIELD_PREP(W0_MASK( 14,   8), v)
50 #define CMD_U0_TID(v)			FIELD_PREP(W0_MASK(  6,   3), v)
56 #define CMD_0_ATTR_A			FIELD_PREP(CMD_0_ATTR, 0x2)
58 #define CMD_A1_DATA_LENGTH(v)		FIELD_PREP(W1_MASK( 53,  32), v)
61 #define CMD_A0_XFER_RATE(v)		FIELD_PREP(W0_MASK( 17,  15), v)
62 #define CMD_A0_ASSIGN_ADDRESS(v)	FIELD_PREP(W0_MASK( 14,   8), v)
63 #define CMD_A0_TID(v)			FIELD_PREP(W0_MASK(  6,   3), v)