Lines Matching refs:master
290 to_dw_i3c_master(struct i3c_master_controller *master) in to_dw_i3c_master() argument
292 return container_of(master, struct dw_i3c_master, base); in to_dw_i3c_master()
295 static void dw_i3c_master_disable(struct dw_i3c_master *master) in dw_i3c_master_disable() argument
297 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, in dw_i3c_master_disable()
298 master->regs + DEVICE_CTRL); in dw_i3c_master_disable()
301 static void dw_i3c_master_enable(struct dw_i3c_master *master) in dw_i3c_master_enable() argument
303 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE, in dw_i3c_master_enable()
304 master->regs + DEVICE_CTRL); in dw_i3c_master_enable()
307 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) in dw_i3c_master_get_addr_pos() argument
311 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_get_addr_pos()
312 if (addr == master->devs[pos].addr) in dw_i3c_master_get_addr_pos()
319 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) in dw_i3c_master_get_free_pos() argument
321 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) in dw_i3c_master_get_free_pos()
324 return ffs(master->free_pos) - 1; in dw_i3c_master_get_free_pos()
327 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, in dw_i3c_master_wr_tx_fifo() argument
330 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); in dw_i3c_master_wr_tx_fifo()
335 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1); in dw_i3c_master_wr_tx_fifo()
339 static void dw_i3c_master_read_fifo(struct dw_i3c_master *master, in dw_i3c_master_read_fifo() argument
342 readsl(master->regs + reg, bytes, nbytes / 4); in dw_i3c_master_read_fifo()
346 readsl(master->regs + reg, &tmp, 1); in dw_i3c_master_read_fifo()
351 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, in dw_i3c_master_read_rx_fifo() argument
354 return dw_i3c_master_read_fifo(master, RX_TX_DATA_PORT, bytes, nbytes); in dw_i3c_master_read_rx_fifo()
357 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master, in dw_i3c_master_read_ibi_fifo() argument
360 return dw_i3c_master_read_fifo(master, IBI_QUEUE_STATUS, bytes, nbytes); in dw_i3c_master_read_ibi_fifo()
364 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) in dw_i3c_master_alloc_xfer() argument
384 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) in dw_i3c_master_start_xfer_locked() argument
386 struct dw_i3c_xfer *xfer = master->xferqueue.cur; in dw_i3c_master_start_xfer_locked()
396 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); in dw_i3c_master_start_xfer_locked()
399 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_start_xfer_locked()
402 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_start_xfer_locked()
407 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); in dw_i3c_master_start_xfer_locked()
408 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); in dw_i3c_master_start_xfer_locked()
412 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, in dw_i3c_master_enqueue_xfer() argument
418 spin_lock_irqsave(&master->xferqueue.lock, flags); in dw_i3c_master_enqueue_xfer()
419 if (master->xferqueue.cur) { in dw_i3c_master_enqueue_xfer()
420 list_add_tail(&xfer->node, &master->xferqueue.list); in dw_i3c_master_enqueue_xfer()
422 master->xferqueue.cur = xfer; in dw_i3c_master_enqueue_xfer()
423 dw_i3c_master_start_xfer_locked(master); in dw_i3c_master_enqueue_xfer()
425 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in dw_i3c_master_enqueue_xfer()
428 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, in dw_i3c_master_dequeue_xfer_locked() argument
431 if (master->xferqueue.cur == xfer) { in dw_i3c_master_dequeue_xfer_locked()
434 master->xferqueue.cur = NULL; in dw_i3c_master_dequeue_xfer_locked()
438 master->regs + RESET_CTRL); in dw_i3c_master_dequeue_xfer_locked()
440 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, in dw_i3c_master_dequeue_xfer_locked()
447 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, in dw_i3c_master_dequeue_xfer() argument
452 spin_lock_irqsave(&master->xferqueue.lock, flags); in dw_i3c_master_dequeue_xfer()
453 dw_i3c_master_dequeue_xfer_locked(master, xfer); in dw_i3c_master_dequeue_xfer()
454 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in dw_i3c_master_dequeue_xfer()
457 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) in dw_i3c_master_end_xfer_locked() argument
459 struct dw_i3c_xfer *xfer = master->xferqueue.cur; in dw_i3c_master_end_xfer_locked()
466 nresp = readl(master->regs + QUEUE_STATUS_LEVEL); in dw_i3c_master_end_xfer_locked()
473 resp = readl(master->regs + RESPONSE_QUEUE_PORT); in dw_i3c_master_end_xfer_locked()
479 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, in dw_i3c_master_end_xfer_locked()
509 dw_i3c_master_dequeue_xfer_locked(master, xfer); in dw_i3c_master_end_xfer_locked()
510 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, in dw_i3c_master_end_xfer_locked()
511 master->regs + DEVICE_CTRL); in dw_i3c_master_end_xfer_locked()
514 xfer = list_first_entry_or_null(&master->xferqueue.list, in dw_i3c_master_end_xfer_locked()
520 master->xferqueue.cur = xfer; in dw_i3c_master_end_xfer_locked()
521 dw_i3c_master_start_xfer_locked(master); in dw_i3c_master_end_xfer_locked()
524 static int dw_i3c_clk_cfg(struct dw_i3c_master *master) in dw_i3c_clk_cfg() argument
530 core_rate = clk_get_rate(master->core_clk); in dw_i3c_clk_cfg()
540 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; in dw_i3c_clk_cfg()
545 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); in dw_i3c_clk_cfg()
551 if (master->base.bus.mode == I3C_BUS_MODE_PURE) in dw_i3c_clk_cfg()
552 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); in dw_i3c_clk_cfg()
557 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); in dw_i3c_clk_cfg()
567 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); in dw_i3c_clk_cfg()
572 static int dw_i2c_clk_cfg(struct dw_i3c_master *master) in dw_i2c_clk_cfg() argument
578 core_rate = clk_get_rate(master->core_clk); in dw_i2c_clk_cfg()
588 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); in dw_i2c_clk_cfg()
594 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); in dw_i2c_clk_cfg()
596 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); in dw_i2c_clk_cfg()
597 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, in dw_i2c_clk_cfg()
598 master->regs + DEVICE_CTRL); in dw_i2c_clk_cfg()
605 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_bus_init() local
611 ret = master->platform_ops->init(master); in dw_i3c_master_bus_init()
618 ret = dw_i2c_clk_cfg(master); in dw_i3c_master_bus_init()
623 ret = dw_i3c_clk_cfg(master); in dw_i3c_master_bus_init()
631 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_bus_init()
637 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_bus_init()
639 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); in dw_i3c_master_bus_init()
641 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); in dw_i3c_master_bus_init()
643 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_bus_init()
644 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); in dw_i3c_master_bus_init()
645 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); in dw_i3c_master_bus_init()
652 master->regs + DEVICE_ADDR); in dw_i3c_master_bus_init()
657 ret = i3c_master_set_info(&master->base, &info); in dw_i3c_master_bus_init()
661 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT); in dw_i3c_master_bus_init()
662 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); in dw_i3c_master_bus_init()
665 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, in dw_i3c_master_bus_init()
666 master->regs + DEVICE_CTRL); in dw_i3c_master_bus_init()
668 dw_i3c_master_enable(master); in dw_i3c_master_bus_init()
675 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_bus_cleanup() local
677 dw_i3c_master_disable(master); in dw_i3c_master_bus_cleanup()
680 static int dw_i3c_ccc_set(struct dw_i3c_master *master, in dw_i3c_ccc_set() argument
688 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); in dw_i3c_ccc_set()
693 xfer = dw_i3c_master_alloc_xfer(master, 1); in dw_i3c_ccc_set()
710 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_ccc_set()
712 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_ccc_set()
723 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) in dw_i3c_ccc_get() argument
729 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); in dw_i3c_ccc_get()
733 xfer = dw_i3c_master_alloc_xfer(master, 1); in dw_i3c_ccc_get()
751 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_ccc_get()
753 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_ccc_get()
766 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_send_ccc_cmd() local
773 ret = dw_i3c_ccc_get(master, ccc); in dw_i3c_master_send_ccc_cmd()
775 ret = dw_i3c_ccc_set(master, ccc); in dw_i3c_master_send_ccc_cmd()
782 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_daa() local
789 olddevs = ~(master->free_pos); in dw_i3c_master_daa()
792 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_daa()
800 master->devs[pos].addr = ret; in dw_i3c_master_daa()
806 master->regs + in dw_i3c_master_daa()
807 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); in dw_i3c_master_daa()
810 xfer = dw_i3c_master_alloc_xfer(master, 1); in dw_i3c_master_daa()
814 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_daa()
821 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | in dw_i3c_master_daa()
828 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_master_daa()
830 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_master_daa()
832 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); in dw_i3c_master_daa()
835 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_daa()
837 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr); in dw_i3c_master_daa()
851 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_priv_xfers() local
859 if (i3c_nxfers > master->caps.cmdfifodepth) in dw_i3c_master_priv_xfers()
869 if (ntxwords > master->caps.datafifodepth || in dw_i3c_master_priv_xfers()
870 nrxwords > master->caps.datafifodepth) in dw_i3c_master_priv_xfers()
873 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); in dw_i3c_master_priv_xfers()
904 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_master_priv_xfers()
906 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_master_priv_xfers()
926 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_reattach_i3c_dev() local
929 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_reattach_i3c_dev()
933 master->regs + in dw_i3c_master_reattach_i3c_dev()
934 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_reattach_i3c_dev()
936 master->devs[data->index].addr = 0; in dw_i3c_master_reattach_i3c_dev()
937 master->free_pos |= BIT(data->index); in dw_i3c_master_reattach_i3c_dev()
940 master->devs[pos].addr = dev->info.dyn_addr; in dw_i3c_master_reattach_i3c_dev()
941 master->free_pos &= ~BIT(pos); in dw_i3c_master_reattach_i3c_dev()
945 master->regs + in dw_i3c_master_reattach_i3c_dev()
946 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_reattach_i3c_dev()
948 master->devs[data->index].addr = dev->info.dyn_addr; in dw_i3c_master_reattach_i3c_dev()
956 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_attach_i3c_dev() local
960 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_attach_i3c_dev()
969 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr; in dw_i3c_master_attach_i3c_dev()
970 master->free_pos &= ~BIT(pos); in dw_i3c_master_attach_i3c_dev()
973 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr), in dw_i3c_master_attach_i3c_dev()
974 master->regs + in dw_i3c_master_attach_i3c_dev()
975 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_attach_i3c_dev()
984 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_detach_i3c_dev() local
987 master->regs + in dw_i3c_master_detach_i3c_dev()
988 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_detach_i3c_dev()
991 master->devs[data->index].addr = 0; in dw_i3c_master_detach_i3c_dev()
992 master->free_pos |= BIT(data->index); in dw_i3c_master_detach_i3c_dev()
1002 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_i2c_xfers() local
1010 if (i2c_nxfers > master->caps.cmdfifodepth) in dw_i3c_master_i2c_xfers()
1020 if (ntxwords > master->caps.datafifodepth || in dw_i3c_master_i2c_xfers()
1021 nrxwords > master->caps.datafifodepth) in dw_i3c_master_i2c_xfers()
1024 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); in dw_i3c_master_i2c_xfers()
1051 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_master_i2c_xfers()
1053 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_master_i2c_xfers()
1064 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_attach_i2c_dev() local
1068 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_attach_i2c_dev()
1077 master->devs[pos].addr = dev->addr; in dw_i3c_master_attach_i2c_dev()
1078 master->free_pos &= ~BIT(pos); in dw_i3c_master_attach_i2c_dev()
1083 master->regs + in dw_i3c_master_attach_i2c_dev()
1084 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_attach_i2c_dev()
1093 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_detach_i2c_dev() local
1096 master->regs + in dw_i3c_master_detach_i2c_dev()
1097 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_detach_i2c_dev()
1100 master->devs[data->index].addr = 0; in dw_i3c_master_detach_i2c_dev()
1101 master->free_pos |= BIT(data->index); in dw_i3c_master_detach_i2c_dev()
1110 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_request_ibi() local
1117 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_request_ibi()
1118 master->devs[data->index].ibi_dev = dev; in dw_i3c_master_request_ibi()
1119 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_request_ibi()
1128 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_free_ibi() local
1131 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_free_ibi()
1132 master->devs[data->index].ibi_dev = NULL; in dw_i3c_master_free_ibi()
1133 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_free_ibi()
1139 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master, in dw_i3c_master_set_sir_enabled() argument
1147 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx); in dw_i3c_master_set_sir_enabled()
1149 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_set_sir_enabled()
1150 reg = readl(master->regs + dat_entry); in dw_i3c_master_set_sir_enabled()
1158 master->platform_ops->set_dat_ibi(master, dev, enable, ®); in dw_i3c_master_set_sir_enabled()
1159 writel(reg, master->regs + dat_entry); in dw_i3c_master_set_sir_enabled()
1161 reg = readl(master->regs + IBI_SIR_REQ_REJECT); in dw_i3c_master_set_sir_enabled()
1166 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK); in dw_i3c_master_set_sir_enabled()
1171 writel(reg, master->regs + IBI_SIR_REQ_REJECT); in dw_i3c_master_set_sir_enabled()
1174 reg = readl(master->regs + INTR_STATUS_EN); in dw_i3c_master_set_sir_enabled()
1178 writel(reg, master->regs + INTR_STATUS_EN); in dw_i3c_master_set_sir_enabled()
1180 reg = readl(master->regs + INTR_SIGNAL_EN); in dw_i3c_master_set_sir_enabled()
1184 writel(reg, master->regs + INTR_SIGNAL_EN); in dw_i3c_master_set_sir_enabled()
1187 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_set_sir_enabled()
1194 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_enable_ibi() local
1197 dw_i3c_master_set_sir_enabled(master, dev, data->index, true); in dw_i3c_master_enable_ibi()
1202 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); in dw_i3c_master_enable_ibi()
1211 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_disable_ibi() local
1218 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); in dw_i3c_master_disable_ibi()
1231 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master, in dw_i3c_master_drain_ibi_queue() argument
1237 readl(master->regs + IBI_QUEUE_STATUS); in dw_i3c_master_drain_ibi_queue()
1240 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master, in dw_i3c_master_handle_ibi_sir() argument
1264 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_handle_ibi_sir()
1265 idx = dw_i3c_master_get_addr_pos(master, addr); in dw_i3c_master_handle_ibi_sir()
1267 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1272 dev = master->devs[idx].ibi_dev; in dw_i3c_master_handle_ibi_sir()
1274 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1282 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1288 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1295 dw_i3c_master_read_ibi_fifo(master, slot->data, len); in dw_i3c_master_handle_ibi_sir()
1300 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_handle_ibi_sir()
1305 dw_i3c_master_drain_ibi_queue(master, len); in dw_i3c_master_handle_ibi_sir()
1307 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_handle_ibi_sir()
1314 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master) in dw_i3c_master_irq_handle_ibis() argument
1319 reg = readl(master->regs + QUEUE_STATUS_LEVEL); in dw_i3c_master_irq_handle_ibis()
1325 reg = readl(master->regs + IBI_QUEUE_STATUS); in dw_i3c_master_irq_handle_ibis()
1328 dw_i3c_master_handle_ibi_sir(master, reg); in dw_i3c_master_irq_handle_ibis()
1331 dev_info(&master->base.dev, in dw_i3c_master_irq_handle_ibis()
1334 dw_i3c_master_drain_ibi_queue(master, len); in dw_i3c_master_irq_handle_ibis()
1341 struct dw_i3c_master *master = dev_id; in dw_i3c_master_irq_handler() local
1344 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1346 if (!(status & readl(master->regs + INTR_STATUS_EN))) { in dw_i3c_master_irq_handler()
1347 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1351 spin_lock(&master->xferqueue.lock); in dw_i3c_master_irq_handler()
1352 dw_i3c_master_end_xfer_locked(master, status); in dw_i3c_master_irq_handler()
1354 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1355 spin_unlock(&master->xferqueue.lock); in dw_i3c_master_irq_handler()
1358 dw_i3c_master_irq_handle_ibis(master); in dw_i3c_master_irq_handler()
1415 int dw_i3c_common_probe(struct dw_i3c_master *master, in dw_i3c_common_probe() argument
1421 if (!master->platform_ops) in dw_i3c_common_probe()
1422 master->platform_ops = &dw_i3c_platform_ops_default; in dw_i3c_common_probe()
1424 master->regs = devm_platform_ioremap_resource(pdev, 0); in dw_i3c_common_probe()
1425 if (IS_ERR(master->regs)) in dw_i3c_common_probe()
1426 return PTR_ERR(master->regs); in dw_i3c_common_probe()
1428 master->core_clk = devm_clk_get(&pdev->dev, NULL); in dw_i3c_common_probe()
1429 if (IS_ERR(master->core_clk)) in dw_i3c_common_probe()
1430 return PTR_ERR(master->core_clk); in dw_i3c_common_probe()
1432 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, in dw_i3c_common_probe()
1434 if (IS_ERR(master->core_rst)) in dw_i3c_common_probe()
1435 return PTR_ERR(master->core_rst); in dw_i3c_common_probe()
1437 ret = clk_prepare_enable(master->core_clk); in dw_i3c_common_probe()
1441 reset_control_deassert(master->core_rst); in dw_i3c_common_probe()
1443 spin_lock_init(&master->xferqueue.lock); in dw_i3c_common_probe()
1444 INIT_LIST_HEAD(&master->xferqueue.list); in dw_i3c_common_probe()
1446 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_common_probe()
1450 dev_name(&pdev->dev), master); in dw_i3c_common_probe()
1454 platform_set_drvdata(pdev, master); in dw_i3c_common_probe()
1457 ret = readl(master->regs + QUEUE_STATUS_LEVEL); in dw_i3c_common_probe()
1458 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); in dw_i3c_common_probe()
1460 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); in dw_i3c_common_probe()
1461 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); in dw_i3c_common_probe()
1463 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); in dw_i3c_common_probe()
1464 master->datstartaddr = ret; in dw_i3c_common_probe()
1465 master->maxdevs = ret >> 16; in dw_i3c_common_probe()
1466 master->free_pos = GENMASK(master->maxdevs - 1, 0); in dw_i3c_common_probe()
1469 if (master->ibi_capable) in dw_i3c_common_probe()
1472 ret = i3c_master_register(&master->base, &pdev->dev, ops, false); in dw_i3c_common_probe()
1479 reset_control_assert(master->core_rst); in dw_i3c_common_probe()
1482 clk_disable_unprepare(master->core_clk); in dw_i3c_common_probe()
1488 void dw_i3c_common_remove(struct dw_i3c_master *master) in dw_i3c_common_remove() argument
1490 i3c_master_unregister(&master->base); in dw_i3c_common_remove()
1492 reset_control_assert(master->core_rst); in dw_i3c_common_remove()
1494 clk_disable_unprepare(master->core_clk); in dw_i3c_common_remove()
1502 struct dw_i3c_master *master; in dw_i3c_probe() local
1504 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); in dw_i3c_probe()
1505 if (!master) in dw_i3c_probe()
1508 return dw_i3c_common_probe(master, pdev); in dw_i3c_probe()
1513 struct dw_i3c_master *master = platform_get_drvdata(pdev); in dw_i3c_remove() local
1515 dw_i3c_common_remove(master); in dw_i3c_remove()