199 	u32		tx_fifo_data;
200 	u32		rx_fifo_data;
247 	u32			bus_err;
249 	u32			qup_err;
256 	u32			config_run;
284 	u32 bus_err;  in qup_i2c_interrupt()
285 	u32 qup_err;  in qup_i2c_interrupt()
286 	u32 opflags;  in qup_i2c_interrupt()
377 				   u32 req_state, u32 req_mask)  in qup_i2c_poll_state_mask()
380 	u32 state;  in qup_i2c_poll_state_mask()
399 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)  in qup_i2c_poll_state()
406 	u32 val = readl(qup->base + QUP_STATE);  in qup_i2c_flush()
422 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)  in qup_i2c_change_state()
438 	u32 status;  in qup_i2c_bus_active()
460 	u32 addr = i2c_8bit_addr_from_msg(msg);  in qup_i2c_write_tx_fifo_v1()
461 	u32 qup_tag;  in qup_i2c_write_tx_fifo_v1()
463 	u32 val;  in qup_i2c_write_tx_fifo_v1()
651 	u32 len = 0, blocks, rem;  in qup_i2c_bam_make_desc()
652 	u32 i = 0, tlen, tx_len = 0;  in qup_i2c_bam_make_desc()
727 	u32 len = 0;  in qup_i2c_bam_schedule_desc()
728 	u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;  in qup_i2c_bam_schedule_desc()
921 	u32 val = 0;  in qup_i2c_read_rx_fifo_v1()
943 	u32 addr, len, val;  in qup_i2c_write_rx_tags_v1()
957 	u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;  in qup_i2c_conf_v1()
958 	u32 io_mode = QUP_REPACK_EN;  in qup_i2c_conf_v1()
1126 	u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;  in qup_i2c_conf_count_v2()
1157 	u32 io_mode = QUP_REPACK_EN;  in qup_i2c_conf_mode_v2()
1604 static u32 qup_i2c_func(struct i2c_adapter *adap)  in qup_i2c_func()
1641 	u32 config;  in qup_i2c_disable_clocks()
1662 	u32 io_mode, hw_ver, size;  in qup_i2c_probe()
1664 	u32 src_clk_freq = DEFAULT_SRC_CLK;  in qup_i2c_probe()
1665 	u32 clk_freq = DEFAULT_CLK_FREQ;  in qup_i2c_probe()