Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
182 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
183 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
283 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt()
288 bus_err = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
289 qup_err = readl(qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
290 opflags = readl(qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
292 if (!qup->msg) { in qup_i2c_interrupt()
294 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
303 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
307 writel(bus_err, qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
310 * Check for BAM mode and returns if already error has come for current in qup_i2c_interrupt()
314 if (qup->use_dma && (qup->qup_err || qup->bus_err)) in qup_i2c_interrupt()
320 * Don’t reset the QUP state in case of BAM mode. The BAM in qup_i2c_interrupt()
322 * which will clear the remaining schedule descriptors in BAM in qup_i2c_interrupt()
323 * HW FIFO and generates the BAM interrupt. in qup_i2c_interrupt()
325 if (!qup->use_dma) in qup_i2c_interrupt()
326 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
334 blk->tx_fifo_free += qup->out_blk_sz; in qup_i2c_interrupt()
335 if (qup->msg->flags & I2C_M_RD) in qup_i2c_interrupt()
336 qup->write_rx_tags(qup); in qup_i2c_interrupt()
338 qup->write_tx_fifo(qup); in qup_i2c_interrupt()
343 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
345 if (!blk->is_rx_blk_mode) { in qup_i2c_interrupt()
346 blk->fifo_available += qup->in_fifo_sz; in qup_i2c_interrupt()
347 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
349 blk->fifo_available += qup->in_blk_sz; in qup_i2c_interrupt()
350 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
354 if (qup->msg->flags & I2C_M_RD) { in qup_i2c_interrupt()
355 if (!blk->rx_bytes_read) in qup_i2c_interrupt()
365 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) in qup_i2c_interrupt()
370 qup->qup_err = qup_err; in qup_i2c_interrupt()
371 qup->bus_err = bus_err; in qup_i2c_interrupt()
372 complete(&qup->xfer); in qup_i2c_interrupt()
387 state = readl(qup->base + QUP_STATE); in qup_i2c_poll_state_mask()
394 } while (retries--); in qup_i2c_poll_state_mask()
396 return -ETIMEDOUT; in qup_i2c_poll_state_mask()
406 u32 val = readl(qup->base + QUP_STATE); in qup_i2c_flush()
409 writel(val, qup->base + QUP_STATE); in qup_i2c_flush()
425 return -EIO; in qup_i2c_change_state()
427 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
430 return -EIO; in qup_i2c_change_state()
443 status = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_bus_active()
448 ret = -ETIMEDOUT; in qup_i2c_bus_active()
458 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1()
459 struct i2c_msg *msg = qup->msg; in qup_i2c_write_tx_fifo_v1()
465 if (qup->pos == 0) { in qup_i2c_write_tx_fifo_v1()
468 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
474 while (blk->tx_fifo_free && qup->pos < msg->len) { in qup_i2c_write_tx_fifo_v1()
475 if (qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
481 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; in qup_i2c_write_tx_fifo_v1()
483 val = qup_tag | msg->buf[qup->pos]; in qup_i2c_write_tx_fifo_v1()
486 if (idx & 1 || qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
487 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v1()
489 qup->pos++; in qup_i2c_write_tx_fifo_v1()
491 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
498 qup->blk.pos = 0; in qup_i2c_set_blk_data()
499 qup->blk.data_len = msg->len; in qup_i2c_set_blk_data()
500 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); in qup_i2c_set_blk_data()
507 if (qup->blk.data_len > qup->blk_xfer_limit) in qup_i2c_get_data_len()
508 data_len = qup->blk_xfer_limit; in qup_i2c_get_data_len()
510 data_len = qup->blk.data_len; in qup_i2c_get_data_len()
517 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); in qup_i2c_check_msg_len()
525 if (qup->is_smbus_read) { in qup_i2c_set_tags_smb()
532 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags_smb()
549 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); in qup_i2c_set_tags()
555 if (qup->blk.pos == 0) { in qup_i2c_set_tags()
559 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags()
565 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
570 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
571 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? in qup_i2c_set_tags()
594 complete(&qup->xfer); in qup_i2c_bam_cb()
604 ret = dma_map_sg(qup->dev, sg, 1, dir); in qup_sg_set_buf()
606 return -EINVAL; in qup_sg_set_buf()
613 if (qup->btx.dma) in qup_i2c_rel_dma()
614 dma_release_channel(qup->btx.dma); in qup_i2c_rel_dma()
615 if (qup->brx.dma) in qup_i2c_rel_dma()
616 dma_release_channel(qup->brx.dma); in qup_i2c_rel_dma()
617 qup->btx.dma = NULL; in qup_i2c_rel_dma()
618 qup->brx.dma = NULL; in qup_i2c_rel_dma()
625 if (!qup->btx.dma) { in qup_i2c_req_dma()
626 qup->btx.dma = dma_request_chan(qup->dev, "tx"); in qup_i2c_req_dma()
627 if (IS_ERR(qup->btx.dma)) { in qup_i2c_req_dma()
628 err = PTR_ERR(qup->btx.dma); in qup_i2c_req_dma()
629 qup->btx.dma = NULL; in qup_i2c_req_dma()
630 dev_err(qup->dev, "\n tx channel not available"); in qup_i2c_req_dma()
635 if (!qup->brx.dma) { in qup_i2c_req_dma()
636 qup->brx.dma = dma_request_chan(qup->dev, "rx"); in qup_i2c_req_dma()
637 if (IS_ERR(qup->brx.dma)) { in qup_i2c_req_dma()
638 dev_err(qup->dev, "\n rx channel not available"); in qup_i2c_req_dma()
639 err = PTR_ERR(qup->brx.dma); in qup_i2c_req_dma()
640 qup->brx.dma = NULL; in qup_i2c_req_dma()
655 qup->blk_xfer_limit = QUP_READ_LIMIT; in qup_i2c_bam_make_desc()
658 blocks = qup->blk.count; in qup_i2c_bam_make_desc()
659 rem = msg->len - (blocks - 1) * limit; in qup_i2c_bam_make_desc()
661 if (msg->flags & I2C_M_RD) { in qup_i2c_bam_make_desc()
662 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
663 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
664 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; in qup_i2c_bam_make_desc()
666 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
669 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
670 &qup->brx.tag.start[0], in qup_i2c_bam_make_desc()
676 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
677 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
684 qup->blk.pos = i; in qup_i2c_bam_make_desc()
686 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
687 &qup->start_tag.start[qup->tag_buf_pos], in qup_i2c_bam_make_desc()
692 qup->tag_buf_pos += len; in qup_i2c_bam_make_desc()
694 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
695 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
696 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; in qup_i2c_bam_make_desc()
698 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
700 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
707 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
708 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
713 qup->blk.pos = i; in qup_i2c_bam_make_desc()
716 qup->tag_buf_pos += tx_len; in qup_i2c_bam_make_desc()
728 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; in qup_i2c_bam_schedule_desc()
733 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; in qup_i2c_bam_schedule_desc()
736 /* scratch buf to read the BAM EOT FLUSH tags */ in qup_i2c_bam_schedule_desc()
737 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], in qup_i2c_bam_schedule_desc()
738 &qup->brx.tag.start[0], in qup_i2c_bam_schedule_desc()
744 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; in qup_i2c_bam_schedule_desc()
745 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], in qup_i2c_bam_schedule_desc()
750 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, in qup_i2c_bam_schedule_desc()
754 dev_err(qup->dev, "failed to get tx desc\n"); in qup_i2c_bam_schedule_desc()
755 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
760 txd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
761 txd->callback_param = qup; in qup_i2c_bam_schedule_desc()
766 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
770 dma_async_issue_pending(qup->btx.dma); in qup_i2c_bam_schedule_desc()
773 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, in qup_i2c_bam_schedule_desc()
777 dev_err(qup->dev, "failed to get rx desc\n"); in qup_i2c_bam_schedule_desc()
778 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
781 dmaengine_terminate_sync(qup->btx.dma); in qup_i2c_bam_schedule_desc()
785 rxd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
786 rxd->callback_param = qup; in qup_i2c_bam_schedule_desc()
789 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
793 dma_async_issue_pending(qup->brx.dma); in qup_i2c_bam_schedule_desc()
796 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) { in qup_i2c_bam_schedule_desc()
797 dev_err(qup->dev, "normal trans timed out\n"); in qup_i2c_bam_schedule_desc()
798 ret = -ETIMEDOUT; in qup_i2c_bam_schedule_desc()
801 if (ret || qup->bus_err || qup->qup_err) { in qup_i2c_bam_schedule_desc()
802 reinit_completion(&qup->xfer); in qup_i2c_bam_schedule_desc()
806 dev_err(qup->dev, "change to run state timed out"); in qup_i2c_bam_schedule_desc()
813 if (!wait_for_completion_timeout(&qup->xfer, HZ)) in qup_i2c_bam_schedule_desc()
814 dev_err(qup->dev, "flush timed out\n"); in qup_i2c_bam_schedule_desc()
816 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_bam_schedule_desc()
820 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
823 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, in qup_i2c_bam_schedule_desc()
831 qup->btx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
832 qup->brx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
833 qup->tag_buf_pos = 0; in qup_i2c_bam_clear_tag_buffers()
843 enable_irq(qup->irq); in qup_i2c_bam_xfer()
849 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_bam_xfer()
850 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_bam_xfer()
852 /* set BAM mode */ in qup_i2c_bam_xfer()
853 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); in qup_i2c_bam_xfer()
856 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); in qup_i2c_bam_xfer()
863 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()
867 qup->msg = msg + idx; in qup_i2c_bam_xfer()
868 qup->is_last = idx == (num - 1); in qup_i2c_bam_xfer()
870 ret = qup_i2c_bam_make_desc(qup, qup->msg); in qup_i2c_bam_xfer()
875 * Make DMA descriptor and schedule the BAM transfer if its in qup_i2c_bam_xfer()
881 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
882 qup->brx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
883 qup->is_last) { in qup_i2c_bam_xfer()
893 disable_irq(qup->irq); in qup_i2c_bam_xfer()
895 qup->msg = NULL; in qup_i2c_bam_xfer()
905 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); in qup_i2c_wait_for_complete()
907 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_wait_for_complete()
908 ret = -ETIMEDOUT; in qup_i2c_wait_for_complete()
911 if (qup->bus_err || qup->qup_err) in qup_i2c_wait_for_complete()
912 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_wait_for_complete()
919 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1()
920 struct i2c_msg *msg = qup->msg; in qup_i2c_read_rx_fifo_v1()
924 while (blk->fifo_available && qup->pos < msg->len) { in qup_i2c_read_rx_fifo_v1()
927 val = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_read_rx_fifo_v1()
928 msg->buf[qup->pos++] = val & 0xFF; in qup_i2c_read_rx_fifo_v1()
930 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; in qup_i2c_read_rx_fifo_v1()
933 blk->fifo_available--; in qup_i2c_read_rx_fifo_v1()
936 if (qup->pos == msg->len) in qup_i2c_read_rx_fifo_v1()
937 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v1()
942 struct i2c_msg *msg = qup->msg; in qup_i2c_write_rx_tags_v1()
948 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; in qup_i2c_write_rx_tags_v1()
951 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v1()
956 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1()
960 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz; in qup_i2c_conf_v1()
961 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz; in qup_i2c_conf_v1()
963 if (blk->is_tx_blk_mode) { in qup_i2c_conf_v1()
965 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
966 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
968 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
969 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
972 if (blk->total_rx_len) { in qup_i2c_conf_v1()
973 if (blk->is_rx_blk_mode) { in qup_i2c_conf_v1()
975 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
976 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
978 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
979 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
985 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_v1()
986 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_v1()
991 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v1()
992 blk->fifo_available = 0; in qup_i2c_clear_blk_v1()
993 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v1()
998 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1()
1007 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()
1013 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v1()
1014 enable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1015 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v1()
1016 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v1()
1028 ret = qup_i2c_wait_for_complete(qup, qup->msg); in qup_i2c_conf_xfer_v1()
1035 disable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1041 struct i2c_msg *msg = qup->msg; in qup_i2c_write_one()
1042 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one()
1044 qup->pos = 0; in qup_i2c_write_one()
1045 blk->total_tx_len = msg->len + 1; in qup_i2c_write_one()
1046 blk->total_rx_len = 0; in qup_i2c_write_one()
1053 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one()
1055 qup->pos = 0; in qup_i2c_read_one()
1056 blk->total_tx_len = 2; in qup_i2c_read_one()
1057 blk->total_rx_len = qup->msg->len; in qup_i2c_read_one()
1069 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer()
1073 qup->bus_err = 0; in qup_i2c_xfer()
1074 qup->qup_err = 0; in qup_i2c_xfer()
1076 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer()
1082 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); in qup_i2c_xfer()
1086 ret = -EIO; in qup_i2c_xfer()
1091 ret = -EINVAL; in qup_i2c_xfer()
1095 qup->msg = &msgs[idx]; in qup_i2c_xfer()
1113 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer()
1114 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer()
1125 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2()
1128 if (blk->is_tx_blk_mode) in qup_i2c_conf_count_v2()
1129 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1130 qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_count_v2()
1132 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1133 qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_count_v2()
1135 if (blk->total_rx_len) { in qup_i2c_conf_count_v2()
1136 if (blk->is_rx_blk_mode) in qup_i2c_conf_count_v2()
1137 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1138 qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_count_v2()
1140 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1141 qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_count_v2()
1146 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_count_v2()
1156 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2()
1159 if (blk->is_tx_blk_mode) { in qup_i2c_conf_mode_v2()
1161 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_mode_v2()
1163 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_mode_v2()
1166 if (blk->is_rx_blk_mode) { in qup_i2c_conf_mode_v2()
1168 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_mode_v2()
1170 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_mode_v2()
1173 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_mode_v2()
1179 blk->send_last_word = false; in qup_i2c_clear_blk_v2()
1180 blk->tx_tags_sent = false; in qup_i2c_clear_blk_v2()
1181 blk->tx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1182 blk->tx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1183 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v2()
1185 blk->rx_tags_fetched = false; in qup_i2c_clear_blk_v2()
1186 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v2()
1187 blk->rx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1188 blk->rx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1189 blk->fifo_available = 0; in qup_i2c_clear_blk_v2()
1195 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data()
1198 for (j = blk->rx_fifo_data_pos; in qup_i2c_recv_data()
1199 blk->cur_blk_len && blk->fifo_available; in qup_i2c_recv_data()
1200 blk->cur_blk_len--, blk->fifo_available--) { in qup_i2c_recv_data()
1202 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_data()
1204 *(blk->cur_data++) = blk->rx_fifo_data; in qup_i2c_recv_data()
1205 blk->rx_fifo_data >>= 8; in qup_i2c_recv_data()
1213 blk->rx_fifo_data_pos = j; in qup_i2c_recv_data()
1219 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_tags()
1221 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_tags()
1222 blk->rx_fifo_data >>= blk->rx_tag_len * 8; in qup_i2c_recv_tags()
1223 blk->rx_fifo_data_pos = blk->rx_tag_len; in qup_i2c_recv_tags()
1224 blk->fifo_available -= blk->rx_tag_len; in qup_i2c_recv_tags()
1237 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v2()
1239 if (!blk->rx_tags_fetched) { in qup_i2c_read_rx_fifo_v2()
1241 blk->rx_tags_fetched = true; in qup_i2c_read_rx_fifo_v2()
1245 if (!blk->cur_blk_len) in qup_i2c_read_rx_fifo_v2()
1246 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v2()
1257 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_blk_data()
1260 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; in qup_i2c_write_blk_data()
1261 (*len)--, blk->tx_fifo_free--) { in qup_i2c_write_blk_data()
1262 blk->tx_fifo_data |= *(*data)++ << (j * 8); in qup_i2c_write_blk_data()
1264 writel(blk->tx_fifo_data, in qup_i2c_write_blk_data()
1265 qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_blk_data()
1266 blk->tx_fifo_data = 0x0; in qup_i2c_write_blk_data()
1273 blk->tx_fifo_data_pos = j; in qup_i2c_write_blk_data()
1279 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_rx_tags_v2()
1281 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); in qup_i2c_write_rx_tags_v2()
1282 if (blk->tx_fifo_data_pos) in qup_i2c_write_rx_tags_v2()
1283 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v2()
1310 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v2()
1312 if (!blk->tx_tags_sent) { in qup_i2c_write_tx_fifo_v2()
1313 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, in qup_i2c_write_tx_fifo_v2()
1314 &blk->tx_tag_len); in qup_i2c_write_tx_fifo_v2()
1315 blk->tx_tags_sent = true; in qup_i2c_write_tx_fifo_v2()
1318 if (blk->send_last_word) in qup_i2c_write_tx_fifo_v2()
1321 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); in qup_i2c_write_tx_fifo_v2()
1322 if (!blk->cur_blk_len) { in qup_i2c_write_tx_fifo_v2()
1323 if (!blk->tx_fifo_data_pos) in qup_i2c_write_tx_fifo_v2()
1326 if (blk->tx_fifo_free) in qup_i2c_write_tx_fifo_v2()
1329 blk->send_last_word = true; in qup_i2c_write_tx_fifo_v2()
1335 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v2()
1347 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v2()
1348 struct i2c_msg *msg = qup->msg; in qup_i2c_conf_xfer_v2()
1357 if (qup->is_smbus_read) { in qup_i2c_conf_xfer_v2()
1363 blk->cur_data += 1; in qup_i2c_conf_xfer_v2()
1370 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; in qup_i2c_conf_xfer_v2()
1381 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()
1388 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v2()
1389 enable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1394 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v2()
1395 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v2()
1419 disable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1432 struct i2c_msg *msg = qup->msg; in qup_i2c_xfer_v2_msg()
1433 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_xfer_v2_msg()
1434 u8 *msg_buf = msg->buf; in qup_i2c_xfer_v2_msg()
1436 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; in qup_i2c_xfer_v2_msg()
1439 for (i = 0; i < blk->count; i++) { in qup_i2c_xfer_v2_msg()
1441 blk->pos = i; in qup_i2c_xfer_v2_msg()
1442 blk->cur_tx_tags = blk->tags; in qup_i2c_xfer_v2_msg()
1443 blk->cur_blk_len = data_len; in qup_i2c_xfer_v2_msg()
1444 blk->tx_tag_len = in qup_i2c_xfer_v2_msg()
1445 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); in qup_i2c_xfer_v2_msg()
1447 blk->cur_data = msg_buf; in qup_i2c_xfer_v2_msg()
1450 blk->total_tx_len = blk->tx_tag_len; in qup_i2c_xfer_v2_msg()
1451 blk->rx_tag_len = 2; in qup_i2c_xfer_v2_msg()
1452 blk->total_rx_len = blk->rx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1454 blk->total_tx_len = blk->tx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1455 blk->total_rx_len = 0; in qup_i2c_xfer_v2_msg()
1459 !qup->is_last || i < blk->count - 1); in qup_i2c_xfer_v2_msg()
1464 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && in qup_i2c_xfer_v2_msg()
1465 !qup->is_smbus_read) { in qup_i2c_xfer_v2_msg()
1466 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) in qup_i2c_xfer_v2_msg()
1467 return -EPROTO; in qup_i2c_xfer_v2_msg()
1469 msg->len = msg->buf[0]; in qup_i2c_xfer_v2_msg()
1470 qup->is_smbus_read = true; in qup_i2c_xfer_v2_msg()
1472 qup->is_smbus_read = false; in qup_i2c_xfer_v2_msg()
1476 msg->len += 1; in qup_i2c_xfer_v2_msg()
1480 blk->data_len -= qup->blk_xfer_limit; in qup_i2c_xfer_v2_msg()
1490 * DMA using BAM : Appropriate for any transaction size but the address should
1525 if (!no_dma && qup->is_dma && in qup_i2c_determine_mode_v2()
1526 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { in qup_i2c_determine_mode_v2()
1527 qup->use_dma = true; in qup_i2c_determine_mode_v2()
1529 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - in qup_i2c_determine_mode_v2()
1531 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - in qup_i2c_determine_mode_v2()
1545 qup->bus_err = 0; in qup_i2c_xfer_v2()
1546 qup->qup_err = 0; in qup_i2c_xfer_v2()
1548 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer_v2()
1556 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer_v2()
1562 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); in qup_i2c_xfer_v2()
1563 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); in qup_i2c_xfer_v2()
1566 ret = -EIO; in qup_i2c_xfer_v2()
1570 if (qup->use_dma) { in qup_i2c_xfer_v2()
1571 reinit_completion(&qup->xfer); in qup_i2c_xfer_v2()
1573 qup->use_dma = false; in qup_i2c_xfer_v2()
1578 qup->msg = &msgs[idx]; in qup_i2c_xfer_v2()
1579 qup->is_last = idx == (num - 1); in qup_i2c_xfer_v2()
1586 qup->msg = NULL; in qup_i2c_xfer_v2()
1598 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer_v2()
1599 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer_v2()
1635 clk_prepare_enable(qup->clk); in qup_i2c_enable_clocks()
1636 clk_prepare_enable(qup->pclk); in qup_i2c_enable_clocks()
1644 clk_disable_unprepare(qup->clk); in qup_i2c_disable_clocks()
1645 config = readl(qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1647 writel(config, qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1648 clk_disable_unprepare(qup->pclk); in qup_i2c_disable_clocks()
1669 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); in qup_i2c_probe()
1671 return -ENOMEM; in qup_i2c_probe()
1673 qup->dev = &pdev->dev; in qup_i2c_probe()
1674 init_completion(&qup->xfer); in qup_i2c_probe()
1678 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); in qup_i2c_probe()
1681 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); in qup_i2c_probe()
1683 dev_notice(qup->dev, "using default clock-frequency %d", in qup_i2c_probe()
1688 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { in qup_i2c_probe()
1689 qup->adap.algo = &qup_i2c_algo; in qup_i2c_probe()
1690 qup->adap.quirks = &qup_i2c_quirks; in qup_i2c_probe()
1693 qup->adap.algo = &qup_i2c_algo_v2; in qup_i2c_probe()
1694 qup->adap.quirks = &qup_i2c_quirks_v2; in qup_i2c_probe()
1696 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) in qup_i2c_probe()
1701 if (ret == -EPROBE_DEFER) in qup_i2c_probe()
1706 qup->max_xfer_sg_len = (MX_BLOCKS << 1); in qup_i2c_probe()
1708 qup->btx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1709 blocks, sizeof(*qup->btx.sg), in qup_i2c_probe()
1711 if (!qup->btx.sg) { in qup_i2c_probe()
1712 ret = -ENOMEM; in qup_i2c_probe()
1715 sg_init_table(qup->btx.sg, blocks); in qup_i2c_probe()
1717 qup->brx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1718 blocks, sizeof(*qup->brx.sg), in qup_i2c_probe()
1720 if (!qup->brx.sg) { in qup_i2c_probe()
1721 ret = -ENOMEM; in qup_i2c_probe()
1724 sg_init_table(qup->brx.sg, blocks); in qup_i2c_probe()
1729 qup->start_tag.start = devm_kzalloc(&pdev->dev, in qup_i2c_probe()
1731 if (!qup->start_tag.start) { in qup_i2c_probe()
1732 ret = -ENOMEM; in qup_i2c_probe()
1736 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1737 if (!qup->brx.tag.start) { in qup_i2c_probe()
1738 ret = -ENOMEM; in qup_i2c_probe()
1742 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1743 if (!qup->btx.tag.start) { in qup_i2c_probe()
1744 ret = -ENOMEM; in qup_i2c_probe()
1747 qup->is_dma = true; in qup_i2c_probe()
1753 dev_err(qup->dev, "clock frequency not supported %d\n", in qup_i2c_probe()
1755 ret = -EINVAL; in qup_i2c_probe()
1759 qup->base = devm_platform_ioremap_resource(pdev, 0); in qup_i2c_probe()
1760 if (IS_ERR(qup->base)) { in qup_i2c_probe()
1761 ret = PTR_ERR(qup->base); in qup_i2c_probe()
1765 qup->irq = platform_get_irq(pdev, 0); in qup_i2c_probe()
1766 if (qup->irq < 0) { in qup_i2c_probe()
1767 ret = qup->irq; in qup_i2c_probe()
1771 if (has_acpi_companion(qup->dev)) { in qup_i2c_probe()
1772 ret = device_property_read_u32(qup->dev, in qup_i2c_probe()
1773 "src-clock-hz", &src_clk_freq); in qup_i2c_probe()
1775 dev_notice(qup->dev, "using default src-clock-hz %d", in qup_i2c_probe()
1778 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); in qup_i2c_probe()
1780 qup->clk = devm_clk_get(qup->dev, "core"); in qup_i2c_probe()
1781 if (IS_ERR(qup->clk)) { in qup_i2c_probe()
1782 dev_err(qup->dev, "Could not get core clock\n"); in qup_i2c_probe()
1783 ret = PTR_ERR(qup->clk); in qup_i2c_probe()
1787 qup->pclk = devm_clk_get(qup->dev, "iface"); in qup_i2c_probe()
1788 if (IS_ERR(qup->pclk)) { in qup_i2c_probe()
1789 dev_err(qup->dev, "Could not get iface clock\n"); in qup_i2c_probe()
1790 ret = PTR_ERR(qup->pclk); in qup_i2c_probe()
1794 src_clk_freq = clk_get_rate(qup->clk); in qup_i2c_probe()
1801 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_probe()
1806 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, in qup_i2c_probe()
1810 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); in qup_i2c_probe()
1814 hw_ver = readl(qup->base + QUP_HW_VERSION); in qup_i2c_probe()
1815 dev_dbg(qup->dev, "Revision %x\n", hw_ver); in qup_i2c_probe()
1817 io_mode = readl(qup->base + QUP_IO_MODE); in qup_i2c_probe()
1825 ret = -EIO; in qup_i2c_probe()
1828 qup->out_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1832 ret = -EIO; in qup_i2c_probe()
1835 qup->in_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1839 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a in qup_i2c_probe()
1843 qup->in_blk_sz /= 2; in qup_i2c_probe()
1844 qup->out_blk_sz /= 2; in qup_i2c_probe()
1845 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; in qup_i2c_probe()
1846 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; in qup_i2c_probe()
1847 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; in qup_i2c_probe()
1849 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; in qup_i2c_probe()
1850 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; in qup_i2c_probe()
1851 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; in qup_i2c_probe()
1855 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); in qup_i2c_probe()
1858 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); in qup_i2c_probe()
1862 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; in qup_i2c_probe()
1863 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1866 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; in qup_i2c_probe()
1867 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1875 qup->one_byte_t = one_bit_t * 9; in qup_i2c_probe()
1876 qup->xfer_timeout = TOUT_MIN * HZ + in qup_i2c_probe()
1877 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); in qup_i2c_probe()
1879 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", in qup_i2c_probe()
1880 qup->in_blk_sz, qup->in_fifo_sz, in qup_i2c_probe()
1881 qup->out_blk_sz, qup->out_fifo_sz); in qup_i2c_probe()
1883 i2c_set_adapdata(&qup->adap, qup); in qup_i2c_probe()
1884 qup->adap.dev.parent = qup->dev; in qup_i2c_probe()
1885 qup->adap.dev.of_node = pdev->dev.of_node; in qup_i2c_probe()
1886 qup->is_last = true; in qup_i2c_probe()
1888 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); in qup_i2c_probe()
1890 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); in qup_i2c_probe()
1891 pm_runtime_use_autosuspend(qup->dev); in qup_i2c_probe()
1892 pm_runtime_set_active(qup->dev); in qup_i2c_probe()
1893 pm_runtime_enable(qup->dev); in qup_i2c_probe()
1895 ret = i2c_add_adapter(&qup->adap); in qup_i2c_probe()
1902 pm_runtime_disable(qup->dev); in qup_i2c_probe()
1903 pm_runtime_set_suspended(qup->dev); in qup_i2c_probe()
1907 if (qup->btx.dma) in qup_i2c_probe()
1908 dma_release_channel(qup->btx.dma); in qup_i2c_probe()
1909 if (qup->brx.dma) in qup_i2c_probe()
1910 dma_release_channel(qup->brx.dma); in qup_i2c_probe()
1918 if (qup->is_dma) { in qup_i2c_remove()
1919 dma_release_channel(qup->btx.dma); in qup_i2c_remove()
1920 dma_release_channel(qup->brx.dma); in qup_i2c_remove()
1923 disable_irq(qup->irq); in qup_i2c_remove()
1925 i2c_del_adapter(&qup->adap); in qup_i2c_remove()
1926 pm_runtime_disable(qup->dev); in qup_i2c_remove()
1927 pm_runtime_set_suspended(qup->dev); in qup_i2c_remove()
1970 { .compatible = "qcom,i2c-qup-v1.1.1" },
1971 { .compatible = "qcom,i2c-qup-v2.1.1" },
1972 { .compatible = "qcom,i2c-qup-v2.2.1" },