i2c/busses/i2c-omap.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
7  * Copyright (C) 2004 - 2007 Texas Instruments.
30 #include <linux/platform_data/i2c-omap.h>
46 /* timeout for pm runtime autosuspend */
203 	unsigned		bb_valid:1;	/* true when BB-bit reflects
268 	writew_relaxed(val, omap->base +
269 			(omap->regs[reg] << omap->reg_shift));
274 	return readw_relaxed(omap->base +
275 				(omap->regs[reg] << omap->reg_shift));
284 	omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
287 	omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
288 	omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
289 	if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
290 		omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
305 	if (omap->iestate)
306 		omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
314 	if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
330 				dev_warn(omap->dev, "timeout waiting "
332 				return -ETIMEDOUT;
340 		if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
341 			/* Schedule I2C-bus monitoring on the next transfer */
342 			omap->bb_valid = 0;
358 	if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
364 		omap->westate = OMAP_I2C_WE_ALL;
367 	if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
374 		fclk = clk_get(omap->dev, "fck");
377 			dev_err(omap->dev, "could not get fck: %i\n", error);
386 		 * between 7 - 12 MHz. The XOR input clock is typically
398 	if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
403 		 * to get longer filter period for better noise suppression.
404 		 * The filter is iclk (fclk for HS) period.
406 		if (omap->speed > 400 ||
407 			       omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
409 		else if (omap->speed > 100)
413 		fclk = clk_get(omap->dev, "fck");
416 			dev_err(omap->dev, "could not get fck: %i\n", error);
425 		psc = psc - 1;
428 		if (omap->speed > 400) {
433 			fsscll = scl - (scl / 3) - 7;
434 			fssclh = (scl / 3) - 5;
437 			scl = fclk_rate / omap->speed;
438 			hsscll = scl - (scl / 3) - 7;
439 			hssclh = (scl / 3) - 5;
440 		} else if (omap->speed > 100) {
444 			scl = internal_clk / omap->speed;
445 			fsscll = scl - (scl / 3) - 7;
446 			fssclh = (scl / 3) - 5;
449 			fsscll = internal_clk / (omap->speed * 2) - 7;
450 			fssclh = internal_clk / (omap->speed * 2) - 5;
459 		scll = fclk_rate / (omap->speed * 2) - 7 + psc;
460 		sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
463 	omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
465 			OMAP_I2C_IE_AL)  | ((omap->fifo_size) ?
468 	omap->pscstate = psc;
469 	omap->scllstate = scll;
470 	omap->sclhstate = sclh;
472 	if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
474 		omap->bb_valid = 1;
494 		return -EBUSY; /* recovery would not fix SCL */
495 	return i2c_recover_bus(&omap->adapter);
516  * Wait while BB-bit doesn't reflect the I2C bus state
518  * In a multimaster environment, after IP software reset, BB-bit value doesn't
519  * correspond to the current bus state. It may happen what BB-bit will be 0,
521  * Here are BB-bit values after reset:
527  * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
528  * combinations on the bus, it set BB-bit to 1.
529  * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
530  * it set BB-bit to 0 and BF to 1.
550 	if (omap->bb_valid)
559 		 * state. BB-bit value is valid.
580 			 * BB-bit value is valid.
594 			dev_warn(omap->dev, "timeout waiting for bus ready\n");
601 	omap->bb_valid = 1;
609 	if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
619 	omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
626 		buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
630 		buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
635 	if (omap->rev < OMAP_I2C_REV_ON_3630)
636 		omap->b_hw = 1; /* Enable hardware fixes */
639 	if (omap->set_mpu_wkup_lat != NULL)
640 		omap->latency = (1000000 * omap->threshold) /
641 			(1000 * omap->speed / 8);
667 	dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
668 		msg->addr, msg->len, msg->flags, stop);
670 	omap->receiver = !!(msg->flags & I2C_M_RD);
671 	omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
673 	omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
676 	omap->buf = msg->buf;
677 	omap->buf_len = msg->len;
679 	/* make sure writes to omap->buf_len are ordered */
682 	omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
690 		reinit_completion(&omap->cmd_complete);
691 	omap->cmd_err = 0;
696 	if (omap->speed > 400)
699 	if (msg->flags & I2C_M_STOP)
701 	if (msg->flags & I2C_M_TEN)
703 	if (!(msg->flags & I2C_M_RD))
706 	if (!omap->b_hw && stop)
718 	if (omap->b_hw && stop) {
726 				dev_err(omap->dev, "controller timed out "
728 				return -ETIMEDOUT;
743 		timeout = wait_for_completion_timeout(&omap->cmd_complete,
749 		} while (ret == -EAGAIN);
755 		dev_err(omap->dev, "controller timed out\n");
758 		return -ETIMEDOUT;
761 	if (likely(!omap->cmd_err))
765 	if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
768 		return -EIO;
771 	if (omap->cmd_err & OMAP_I2C_STAT_AL)
772 		return -EAGAIN;
774 	if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
775 		if (msg->flags & I2C_M_IGNORE_NAK)
781 		return -EREMOTEIO;
783 	return -EIO;
799 	r = pm_runtime_get_sync(omap->dev);
811 	if (omap->set_mpu_wkup_lat != NULL)
812 		omap->set_mpu_wkup_lat(omap->dev, omap->latency);
815 		r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
826 	if (omap->set_mpu_wkup_lat != NULL)
827 		omap->set_mpu_wkup_lat(omap->dev, -1);
830 	pm_runtime_mark_last_busy(omap->dev);
831 	pm_runtime_put_autosuspend(omap->dev);
857 	omap->cmd_err |= err;
858 	complete(&omap->cmd_complete);
888 				dev_dbg(omap->dev, "RDR when bus is busy.\n");
904 	if (pm_runtime_suspended(omap->dev))
912 		dev_err(omap->dev, "Arbitration lost\n");
923 		if (omap->buf_len) {
925 			*omap->buf++ = w;
926 			omap->buf_len--;
927 			if (omap->buf_len) {
928 				*omap->buf++ = w >> 8;
929 				omap->buf_len--;
932 			dev_err(omap->dev, "RRDY IRQ while no data requested\n");
935 		if (omap->buf_len) {
936 			w = *omap->buf++;
937 			omap->buf_len--;
938 			if (omap->buf_len) {
939 				w |= *omap->buf++ << 8;
940 				omap->buf_len--;
944 			dev_err(omap->dev, "XRDY IRQ while no data to send\n");
975 				omap->cmd_err |= OMAP_I2C_STAT_NACK;
980 				dev_err(omap->dev, "Arbitration lost\n");
981 				omap->cmd_err |= OMAP_I2C_STAT_AL;
985 			return -EIO;
989 	} while (--timeout);
992 		dev_err(omap->dev, "timeout waiting on XUDF bit\n");
1004 	while (num_bytes--) {
1006 		*omap->buf++ = w;
1007 		omap->buf_len--;
1013 		if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1014 			*omap->buf++ = w >> 8;
1015 			omap->buf_len--;
1025 	while (num_bytes--) {
1026 		w = *omap->buf++;
1027 		omap->buf_len--;
1033 		if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1034 			w |= *omap->buf++ << 8;
1035 			omap->buf_len--;
1038 		if (omap->errata & I2C_OMAP_ERRATA_I462) {
1064 		if (omap->receiver)
1071 			err = -EAGAIN;
1075 		dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1077 			dev_warn(omap->dev, "Too much work in one IRQ\n");
1082 			omap->cmd_err |= OMAP_I2C_STAT_NACK;
1086 				err = -EAGAIN;
1092 			dev_err(omap->dev, "Arbitration lost\n");
1116 			if (omap->fifo_size)
1117 				num_bytes = omap->buf_len;
1119 			if (omap->errata & I2C_OMAP_ERRATA_I207) {
1133 			if (omap->threshold)
1134 				num_bytes = omap->threshold;
1145 			if (omap->fifo_size)
1146 				num_bytes = omap->buf_len;
1160 			if (omap->threshold)
1161 				num_bytes = omap->threshold;
1172 			dev_err(omap->dev, "Receive overrun\n");
1179 			dev_err(omap->dev, "Transmit underflow\n");
1196 	if (ret != -EAGAIN)
1238 		.compatible = "ti,omap4-i2c",
1242 		.compatible = "ti,omap3-i2c",
1246 		.compatible = "ti,omap2430-i2c",
1250 		.compatible = "ti,omap2420-i2c",
1311 	/* set SCL to high-impedance state (reset value is 0) */
1313 	/* set SDA to high-impedance state (reset value is 0) */
1347 		dev_get_platdata(&pdev->dev);
1348 	struct device_node	*node = pdev->dev.of_node;
1359 	omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1361 		return -ENOMEM;
1363 	omap->base = devm_platform_ioremap_resource(pdev, 0);
1364 	if (IS_ERR(omap->base))
1365 		return PTR_ERR(omap->base);
1367 	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1371 		pdata = match->data;
1372 		omap->flags = pdata->flags;
1374 		of_property_read_u32(node, "clock-frequency", &freq);
1376 		omap->speed = freq / 1000;
1378 		omap->speed = pdata->clkrate;
1379 		omap->flags = pdata->flags;
1380 		omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1383 	omap->dev = &pdev->dev;
1384 	omap->irq = irq;
1387 	init_completion(&omap->cmd_complete);
1389 	omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1391 	pm_runtime_enable(omap->dev);
1392 	pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1393 	pm_runtime_use_autosuspend(omap->dev);
1395 	r = pm_runtime_resume_and_get(omap->dev);
1400 	 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1405 	rev = readw_relaxed(omap->base + 0x04);
1407 	omap->scheme = OMAP_I2C_SCHEME(rev);
1408 	switch (omap->scheme) {
1410 		omap->regs = (u8 *)reg_map_ip_v1;
1411 		omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1412 		minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1413 		major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1417 		omap->regs = (u8 *)reg_map_ip_v2;
1422 		omap->rev = rev;
1425 	omap->errata = 0;
1427 	if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1428 			omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1429 		omap->errata |= I2C_OMAP_ERRATA_I207;
1431 	if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1432 		omap->errata |= I2C_OMAP_ERRATA_I462;
1434 	if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1437 		/* Set up the fifo size - Get total size */
1439 		omap->fifo_size = 0x8 << s;
1447 		omap->fifo_size = (omap->fifo_size / 2);
1449 		if (omap->rev < OMAP_I2C_REV_ON_3630)
1450 			omap->b_hw = 1; /* Enable hardware fixes */
1453 		if (omap->set_mpu_wkup_lat != NULL)
1454 			omap->latency = (1000000 * omap->fifo_size) /
1455 				       (1000 * omap->speed / 8);
1461 	if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1462 		r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1463 				IRQF_NO_SUSPEND, pdev->name, omap);
1465 		r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1468 				pdev->name, omap);
1471 		dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1475 	adap = &omap->adapter;
1477 	adap->owner = THIS_MODULE;
1478 	adap->class = I2C_CLASS_DEPRECATED;
1479 	strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1480 	adap->algo = &omap_i2c_algo;
1481 	adap->quirks = &omap_i2c_quirks;
1482 	adap->dev.parent = &pdev->dev;
1483 	adap->dev.of_node = pdev->dev.of_node;
1484 	adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1487 	adap->nr = pdev->id;
1492 	dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1493 		 major, minor, omap->speed);
1495 	pm_runtime_mark_last_busy(omap->dev);
1496 	pm_runtime_put_autosuspend(omap->dev);
1502 	pm_runtime_dont_use_autosuspend(omap->dev);
1503 	pm_runtime_put_sync(omap->dev);
1505 	pm_runtime_disable(&pdev->dev);
1515 	i2c_del_adapter(&omap->adapter);
1517 	ret = pm_runtime_get_sync(&pdev->dev);
1519 		dev_err(omap->dev, "Failed to resume hardware, skip disable\n");
1523 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1524 	pm_runtime_put_sync(&pdev->dev);
1525 	pm_runtime_disable(&pdev->dev);
1532 	omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1534 	if (omap->scheme == OMAP_I2C_SCHEME_0)
1540 	if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1543 		omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1560 	if (!omap->regs)