124 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */  macro
484 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
486 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
672 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_reset()
1066 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1091 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1138 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1146 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {  in npcm_i2c_int_slave_handler()
1155 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1432 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1434 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1483 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_nack()
1602 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1607 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1611 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1724 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
1727 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
2070 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()
2073 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()