99 #define NPCM_I2CCTL1			0x06  macro
445 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_eob_int()
451 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_eob_int()
511 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_int_enable()
517 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_int_enable()
524 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_start()
527 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_start()
540 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_stop()
543 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_stop()
562 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_stall_after_start()
568 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_stall_after_start()
575 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_nack()
578 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_nack()
596 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_int_enable()
602 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_int_enable()
614 		i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_enable()
619 		iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_enable()
655 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_reset()
662 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_reset()
1668 		       ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&  in npcm_i2c_int_master_handler()
1966 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_init_module()
1968 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_init_module()