Lines Matching +full:i2c +full:- +full:sda +full:- +full:hold +full:- +full:time +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
25 #include "i2c-designware-core.h"
34 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
35 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
37 /* Configure the I2C master */ in i2c_dw_configure_fifo_master()
38 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
45 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
54 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
60 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
61 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
64 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
66 dev->ss_hcnt = in i2c_dw_set_timings_master()
72 dev->ss_lcnt = in i2c_dw_set_timings_master()
78 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
79 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
86 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { in i2c_dw_set_timings_master()
91 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
92 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
93 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
96 dev->fs_hcnt = in i2c_dw_set_timings_master()
98 260, /* tHIGH = 260 ns */ in i2c_dw_set_timings_master()
102 dev->fs_lcnt = in i2c_dw_set_timings_master()
104 500, /* tLOW = 500 ns */ in i2c_dw_set_timings_master()
114 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
116 dev->fs_hcnt = in i2c_dw_set_timings_master()
122 dev->fs_lcnt = in i2c_dw_set_timings_master()
128 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
129 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
132 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
136 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
137 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_set_timings_master()
138 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
139 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
140 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
141 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
142 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
144 dev->hs_hcnt = in i2c_dw_set_timings_master()
146 160, /* tHIGH = 160 ns */ in i2c_dw_set_timings_master()
150 dev->hs_lcnt = in i2c_dw_set_timings_master()
152 320, /* tLOW = 320 ns */ in i2c_dw_set_timings_master()
156 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
157 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
164 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); in i2c_dw_set_timings_master()
169 * i2c_dw_init_master() - Initialize the designware I2C master hardware
172 * This functions configures and enables the I2C master.
173 * This function is called during I2C init function, and in case of timeout at
174 * run time.
188 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
189 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
192 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
193 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
196 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
197 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
198 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
201 /* Write SDA hold time if supported */ in i2c_dw_init_master()
202 if (dev->sda_hold_time) in i2c_dw_init_master()
203 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
213 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
221 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
224 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
232 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
236 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
239 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
240 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
243 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_xfer_init()
249 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
252 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
253 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK); in i2c_dw_xfer_init()
257 * This function waits for the controller to be idle before disabling I2C
275 regmap_read(dev->map, DW_IC_STATUS, &status); in i2c_dw_is_controller_active()
279 return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, in i2c_dw_is_controller_active()
289 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, in i2c_dw_check_stopbit()
293 dev_err(dev->dev, "i2c timeout error %d\n", ret); in i2c_dw_check_stopbit()
326 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); in amd_i2c_dw_xfer_quirk()
328 dev->msgs = msgs; in amd_i2c_dw_xfer_quirk()
329 dev->msgs_num = num_msgs; in amd_i2c_dw_xfer_quirk()
331 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in amd_i2c_dw_xfer_quirk()
339 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); in amd_i2c_dw_xfer_quirk()
341 * Initiate the i2c read/write transaction of buffer length, in amd_i2c_dw_xfer_quirk()
345 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { in amd_i2c_dw_xfer_quirk()
346 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) in amd_i2c_dw_xfer_quirk()
351 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); in amd_i2c_dw_xfer_quirk()
352 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); in amd_i2c_dw_xfer_quirk()
354 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
355 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
366 regmap_read(dev->map, DW_IC_DATA_CMD, &val); in amd_i2c_dw_xfer_quirk()
374 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); in amd_i2c_dw_xfer_quirk()
390 return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val, in i2c_dw_poll_tx_empty()
399 return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val, in i2c_dw_poll_rx_full()
412 dev->msgs = msgs; in txgbe_i2c_dw_xfer_quirk()
413 dev->msgs_num = num_msgs; in txgbe_i2c_dw_xfer_quirk()
415 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in txgbe_i2c_dw_xfer_quirk()
422 if (msg_idx == num_msgs - 1 && data_idx == buf_len - 1) in txgbe_i2c_dw_xfer_quirk()
426 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | stop); in txgbe_i2c_dw_xfer_quirk()
432 regmap_read(dev->map, DW_IC_DATA_CMD, &val); in txgbe_i2c_dw_xfer_quirk()
439 regmap_write(dev->map, DW_IC_DATA_CMD, in txgbe_i2c_dw_xfer_quirk()
457 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
460 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
461 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
462 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
468 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
469 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
473 * reprogram the target address in the I2C in i2c_dw_xfer_msg()
476 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
477 dev_err(dev->dev, in i2c_dw_xfer_msg()
479 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
483 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
485 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
486 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
492 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
493 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
497 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
498 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
500 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
501 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
514 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
519 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
528 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
531 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
534 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
536 rx_limit--; in i2c_dw_xfer_msg()
537 dev->rx_outstanding++; in i2c_dw_xfer_msg()
539 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
542 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
545 dev->tx_buf = buf; in i2c_dw_xfer_msg()
546 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
556 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
561 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
564 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
571 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
574 if (dev->msg_err) in i2c_dw_xfer_msg()
577 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask); in i2c_dw_xfer_msg()
583 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
584 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
591 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
592 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
593 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
596 * Received buffer length, re-enable TX_EMPTY interrupt in i2c_dw_recv_len()
599 regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY, in i2c_dw_recv_len()
608 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
611 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
616 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
619 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
620 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
621 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
623 len = dev->rx_buf_len; in i2c_dw_read()
624 buf = dev->rx_buf; in i2c_dw_read()
627 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
629 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
630 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
632 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
651 dev->rx_outstanding--; in i2c_dw_read()
655 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
656 dev->rx_buf_len = len; in i2c_dw_read()
657 dev->rx_buf = buf; in i2c_dw_read()
660 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
673 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
675 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
678 * Initiate I2C message transfer when polling mode is enabled, in i2c_dw_xfer()
682 switch (dev->flags & MODEL_MASK) { in i2c_dw_xfer()
693 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
694 dev->msgs = msgs; in i2c_dw_xfer()
695 dev->msgs_num = num; in i2c_dw_xfer()
696 dev->cmd_err = 0; in i2c_dw_xfer()
697 dev->msg_write_idx = 0; in i2c_dw_xfer()
698 dev->msg_read_idx = 0; in i2c_dw_xfer()
699 dev->msg_err = 0; in i2c_dw_xfer()
700 dev->status = 0; in i2c_dw_xfer()
701 dev->abort_source = 0; in i2c_dw_xfer()
702 dev->rx_outstanding = 0; in i2c_dw_xfer()
716 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { in i2c_dw_xfer()
717 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
719 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
721 ret = -ETIMEDOUT; in i2c_dw_xfer()
730 * controller is still ACTIVE before disabling I2C. in i2c_dw_xfer()
733 dev_err(dev->dev, "controller active\n"); in i2c_dw_xfer()
745 if (dev->msg_err) { in i2c_dw_xfer()
746 ret = dev->msg_err; in i2c_dw_xfer()
751 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
757 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
762 if (dev->status) in i2c_dw_xfer()
763 dev_err(dev->dev, in i2c_dw_xfer()
764 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
766 ret = -EIO; in i2c_dw_xfer()
772 pm_runtime_mark_last_busy(dev->dev); in i2c_dw_xfer()
773 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
803 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
810 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
813 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
815 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
817 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
819 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
825 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
826 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
829 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
831 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
833 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) in i2c_dw_read_clear_intrbits()
834 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
836 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
838 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
844 * Interrupt service routine. This gets called whenever an I2C master interrupt
852 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
853 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
856 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0)) in i2c_dw_isr()
858 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
862 if (!(dev->status & STATUS_ACTIVE)) { in i2c_dw_isr()
870 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_isr()
875 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_isr()
876 dev->status &= ~STATUS_MASK; in i2c_dw_isr()
877 dev->rx_outstanding = 0; in i2c_dw_isr()
883 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_isr()
900 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && in i2c_dw_isr()
901 (dev->rx_outstanding == 0)) in i2c_dw_isr()
902 complete(&dev->cmd_complete); in i2c_dw_isr()
903 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_isr()
905 regmap_read(dev->map, DW_IC_INTR_MASK, &stat); in i2c_dw_isr()
906 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_isr()
907 regmap_write(dev->map, DW_IC_INTR_MASK, stat); in i2c_dw_isr()
915 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
917 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
919 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
922 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
924 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
926 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
929 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
932 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
942 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
951 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
957 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
958 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
961 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
965 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
967 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
970 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
972 rinfo->pinctrl = devm_pinctrl_get(dev->dev); in i2c_dw_init_recovery_info()
973 if (IS_ERR(rinfo->pinctrl)) { in i2c_dw_init_recovery_info()
974 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) in i2c_dw_init_recovery_info()
975 return PTR_ERR(rinfo->pinctrl); in i2c_dw_init_recovery_info()
977 rinfo->pinctrl = NULL; in i2c_dw_init_recovery_info()
978 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n"); in i2c_dw_init_recovery_info()
979 } else if (!rinfo->pinctrl) { in i2c_dw_init_recovery_info()
980 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n"); in i2c_dw_init_recovery_info()
983 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
984 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
985 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
986 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
988 dev_info(dev->dev, "running with gpio recovery mode! scl%s", in i2c_dw_init_recovery_info()
989 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
996 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_poll_adap_quirk()
999 pm_runtime_get_noresume(dev->dev); in i2c_dw_poll_adap_quirk()
1002 dev_err(dev->dev, "Failed to add adapter: %d\n", ret); in i2c_dw_poll_adap_quirk()
1003 pm_runtime_put_noidle(dev->dev); in i2c_dw_poll_adap_quirk()
1010 switch (dev->flags & MODEL_MASK) { in i2c_dw_is_model_poll()
1021 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
1026 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
1028 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
1029 dev->disable = i2c_dw_disable; in i2c_dw_probe_master()
1050 * and enables the SCL/SDA stuck low. SMU FW does the in i2c_dw_probe_master()
1054 ret = regmap_read(dev->map, DW_IC_CON, &ic_con); in i2c_dw_probe_master()
1060 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; in i2c_dw_probe_master()
1062 ret = dev->init(dev); in i2c_dw_probe_master()
1066 snprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
1067 "Synopsys DesignWare I2C adapter"); in i2c_dw_probe_master()
1068 adap->retries = 3; in i2c_dw_probe_master()
1069 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
1070 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
1071 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
1077 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
1087 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_probe_master()
1090 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, in i2c_dw_probe_master()
1091 dev_name(dev->dev), dev); in i2c_dw_probe_master()
1093 dev_err(dev->dev, "failure requesting irq %i: %d\n", in i2c_dw_probe_master()
1094 dev->irq, ret); in i2c_dw_probe_master()
1106 * registered I2C slaves that do I2C transfers in their probe. in i2c_dw_probe_master()
1108 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
1111 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
1112 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()
1118 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");