33 	struct gth_device	*gth;  member
61 static void gth_output_set(struct gth_device *gth, int port,  in gth_output_set()  argument
68 	val = ioread32(gth->base + reg);  in gth_output_set()
71 	iowrite32(val, gth->base + reg);  in gth_output_set()
74 static unsigned int gth_output_get(struct gth_device *gth, int port)  in gth_output_get()  argument
80 	val = ioread32(gth->base + reg);  in gth_output_get()
87 static void gth_smcfreq_set(struct gth_device *gth, int port,  in gth_smcfreq_set()  argument
94 	val = ioread32(gth->base + reg);  in gth_smcfreq_set()
97 	iowrite32(val, gth->base + reg);  in gth_smcfreq_set()
100 static unsigned int gth_smcfreq_get(struct gth_device *gth, int port)  in gth_smcfreq_get()  argument
106 	val = ioread32(gth->base + reg);  in gth_smcfreq_get()
119 	struct gth_device	*gth;  member
124 gth_master_set(struct gth_device *gth, unsigned int master, int port)  in gth_master_set()  argument
135 	val = ioread32(gth->base + reg);  in gth_master_set()
139 	iowrite32(val, gth->base + reg);  in gth_master_set()
148 	struct gth_device *gth = ma->gth;  in master_attr_show()  local
152 	spin_lock(&gth->gth_lock);  in master_attr_show()
153 	port = gth->master[ma->master];  in master_attr_show()
154 	spin_unlock(&gth->gth_lock);  in master_attr_show()
170 	struct gth_device *gth = ma->gth;  in master_attr_store()  local
179 	spin_lock(&gth->gth_lock);  in master_attr_store()
182 	old_port = gth->master[ma->master];  in master_attr_store()
184 		gth->master[ma->master] = -1;  in master_attr_store()
185 		clear_bit(ma->master, gth->output[old_port].master);  in master_attr_store()
191 		if (gth->output[old_port].output->active)  in master_attr_store()
192 			gth_master_set(gth, ma->master, -1);  in master_attr_store()
198 		if (!gth->output[port].output) {  in master_attr_store()
203 		set_bit(ma->master, gth->output[port].master);  in master_attr_store()
206 		if (gth->output[port].output->active)  in master_attr_store()
207 			gth_master_set(gth, ma->master, port);  in master_attr_store()
210 	gth->master[ma->master] = port;  in master_attr_store()
213 	spin_unlock(&gth->gth_lock);  in master_attr_store()
220 	struct gth_device	*gth;  member
235 	unsigned int	(*get)(struct gth_device *gth, int port);
236 	void		(*set)(struct gth_device *gth, int port,
251 gth_output_parm_set(struct gth_device *gth, int port, unsigned int parm,  in gth_output_parm_set()  argument
254 	unsigned int config = output_parms[parm].get(gth, port);  in gth_output_parm_set()
260 	output_parms[parm].set(gth, port, config);  in gth_output_parm_set()
264 gth_output_parm_get(struct gth_device *gth, int port, unsigned int parm)  in gth_output_parm_get()  argument
266 	unsigned int config = output_parms[parm].get(gth, port);  in gth_output_parm_get()
278 static int intel_th_gth_reset(struct gth_device *gth)  in intel_th_gth_reset()  argument
283 	reg = ioread32(gth->base + REG_GTH_SCRPD0);  in intel_th_gth_reset()
289 	iowrite32(reg, gth->base + REG_GTH_SCRPD0);  in intel_th_gth_reset()
293 		if (gth_output_parm_get(gth, port, TH_OUTPUT_PARM(port)) ==  in intel_th_gth_reset()
297 		gth_output_set(gth, port, 0);  in intel_th_gth_reset()
298 		gth_smcfreq_set(gth, port, 16);  in intel_th_gth_reset()
301 	iowrite32(0, gth->base + REG_GTH_DESTOVR);  in intel_th_gth_reset()
305 		iowrite32(0, gth->base + REG_GTH_SWDEST0 + i * 4);  in intel_th_gth_reset()
308 	iowrite32(0, gth->base + REG_GTH_SCR);  in intel_th_gth_reset()
309 	iowrite32(0xfc, gth->base + REG_GTH_SCR2);  in intel_th_gth_reset()
312 	iowrite32(CTS_EVENT_ENABLE_IF_ANYTHING, gth->base + REG_CTS_C0S0_EN);  in intel_th_gth_reset()
314 		  CTS_ACTION_CONTROL_TRIGGER, gth->base + REG_CTS_C0S0_ACT);  in intel_th_gth_reset()
329 	struct gth_device *gth = oa->gth;  in output_attr_show()  local
334 	spin_lock(&gth->gth_lock);  in output_attr_show()
336 			 gth_output_parm_get(gth, oa->port, oa->parm));  in output_attr_show()
337 	spin_unlock(&gth->gth_lock);  in output_attr_show()
350 	struct gth_device *gth = oa->gth;  in output_attr_store()  local
358 	spin_lock(&gth->gth_lock);  in output_attr_store()
359 	gth_output_parm_set(gth, oa->port, oa->parm, config);  in output_attr_store()
360 	spin_unlock(&gth->gth_lock);  in output_attr_store()
367 static int intel_th_master_attributes(struct gth_device *gth)  in intel_th_master_attributes()  argument
373 	attrs = devm_kcalloc(gth->dev, nattrs, sizeof(void *), GFP_KERNEL);  in intel_th_master_attributes()
377 	master_attrs = devm_kcalloc(gth->dev, nattrs,  in intel_th_master_attributes()
386 		name = devm_kasprintf(gth->dev, GFP_KERNEL, "%d%s", i,  in intel_th_master_attributes()
399 		master_attrs[i].gth = gth;  in intel_th_master_attributes()
403 	gth->master_group.name	= "masters";  in intel_th_master_attributes()
404 	gth->master_group.attrs = attrs;  in intel_th_master_attributes()
406 	return sysfs_create_group(&gth->dev->kobj, &gth->master_group);  in intel_th_master_attributes()
409 static int intel_th_output_attributes(struct gth_device *gth)  in intel_th_output_attributes()  argument
417 	attrs = devm_kcalloc(gth->dev, nattrs, sizeof(void *), GFP_KERNEL);  in intel_th_output_attributes()
421 	out_attrs = devm_kcalloc(gth->dev, nattrs,  in intel_th_output_attributes()
432 			name = devm_kasprintf(gth->dev, GFP_KERNEL, "%d_%s", i,  in intel_th_output_attributes()
452 			out_attrs[idx].gth = gth;  in intel_th_output_attributes()
458 	gth->output_group.name	= "outputs";  in intel_th_output_attributes()
459 	gth->output_group.attrs = attrs;  in intel_th_output_attributes()
461 	return sysfs_create_group(&gth->dev->kobj, &gth->output_group);  in intel_th_output_attributes()
473 static void intel_th_gth_stop(struct gth_device *gth,  in intel_th_gth_stop()  argument
485 	iowrite32(0, gth->base + REG_GTH_SCR);  in intel_th_gth_stop()
486 	iowrite32(scr2, gth->base + REG_GTH_SCR2);  in intel_th_gth_stop()
491 		reg = ioread32(gth->base + REG_GTH_STAT);  in intel_th_gth_stop()
496 		dev_dbg(gth->dev, "timeout waiting for GTH[%d] PLE\n",  in intel_th_gth_stop()
504 	iowrite32(0xfc, gth->base + REG_GTH_SCR2);  in intel_th_gth_stop()
514 static void intel_th_gth_start(struct gth_device *gth,  in intel_th_gth_start()  argument
522 	iowrite32(scr, gth->base + REG_GTH_SCR);  in intel_th_gth_start()
523 	iowrite32(0, gth->base + REG_GTH_SCR2);  in intel_th_gth_start()
538 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_disable()  local
542 	spin_lock(&gth->gth_lock);  in intel_th_gth_disable()
545 	for_each_set_bit(master, gth->output[output->port].master,  in intel_th_gth_disable()
547 		gth_master_set(gth, master, -1);  in intel_th_gth_disable()
549 	spin_unlock(&gth->gth_lock);  in intel_th_gth_disable()
551 	intel_th_gth_stop(gth, output, true);  in intel_th_gth_disable()
553 	reg = ioread32(gth->base + REG_GTH_SCRPD0);  in intel_th_gth_disable()
555 	iowrite32(reg, gth->base + REG_GTH_SCRPD0);  in intel_th_gth_disable()
558 static void gth_tscu_resync(struct gth_device *gth)  in gth_tscu_resync()  argument
562 	reg = ioread32(gth->base + REG_TSCU_TSUCTRL);  in gth_tscu_resync()
564 	iowrite32(reg, gth->base + REG_TSCU_TSUCTRL);  in gth_tscu_resync()
570 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_prepare()  local
578 	     count && !(gth_output_get(gth, output->port) & BIT(5)); count--)  in intel_th_gth_prepare()
593 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_enable()  local
598 	spin_lock(&gth->gth_lock);  in intel_th_gth_enable()
599 	for_each_set_bit(master, gth->output[output->port].master,  in intel_th_gth_enable()
601 		gth_master_set(gth, master, output->port);  in intel_th_gth_enable()
605 	spin_unlock(&gth->gth_lock);  in intel_th_gth_enable()
608 		gth_tscu_resync(gth);  in intel_th_gth_enable()
610 	scrpd = ioread32(gth->base + REG_GTH_SCRPD0);  in intel_th_gth_enable()
612 	iowrite32(scrpd, gth->base + REG_GTH_SCRPD0);  in intel_th_gth_enable()
614 	intel_th_gth_start(gth, output);  in intel_th_gth_enable()
628 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_switch()  local
633 	iowrite32(0, gth->base + REG_CTS_CTL);  in intel_th_gth_switch()
634 	iowrite32(CTS_CTL_SEQUENCER_ENABLE, gth->base + REG_CTS_CTL);  in intel_th_gth_switch()
638 		reg = ioread32(gth->base + REG_CTS_STAT);  in intel_th_gth_switch()
645 	iowrite32(0, gth->base + REG_CTS_CTL);  in intel_th_gth_switch()
647 	intel_th_gth_stop(gth, output, false);  in intel_th_gth_switch()
648 	intel_th_gth_start(gth, output);  in intel_th_gth_switch()
665 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_assign()  local
675 		if (gth->output[i].port_type != othdev->output.type)  in intel_th_gth_assign()
687 	spin_lock(&gth->gth_lock);  in intel_th_gth_assign()
690 	gth->output[i].output = &othdev->output;  in intel_th_gth_assign()
691 	spin_unlock(&gth->gth_lock);  in intel_th_gth_assign()
704 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_unassign()  local
711 	spin_lock(&gth->gth_lock);  in intel_th_gth_unassign()
714 	gth->output[port].output = NULL;  in intel_th_gth_unassign()
716 		if (gth->master[master] == port)  in intel_th_gth_unassign()
717 			gth->master[master] = -1;  in intel_th_gth_unassign()
718 	spin_unlock(&gth->gth_lock);  in intel_th_gth_unassign()
724 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_set_output()  local
734 	spin_lock(&gth->gth_lock);  in intel_th_gth_set_output()
735 	if (gth->master[master] == -1) {  in intel_th_gth_set_output()
736 		set_bit(master, gth->output[port].master);  in intel_th_gth_set_output()
737 		gth->master[master] = port;  in intel_th_gth_set_output()
739 	spin_unlock(&gth->gth_lock);  in intel_th_gth_set_output()
748 	struct gth_device *gth;  in intel_th_gth_probe()  local
761 	gth = devm_kzalloc(dev, sizeof(*gth), GFP_KERNEL);  in intel_th_gth_probe()
762 	if (!gth)  in intel_th_gth_probe()
765 	gth->dev = dev;  in intel_th_gth_probe()
766 	gth->base = base;  in intel_th_gth_probe()
767 	spin_lock_init(&gth->gth_lock);  in intel_th_gth_probe()
769 	dev_set_drvdata(dev, gth);  in intel_th_gth_probe()
780 	ret = intel_th_gth_reset(gth);  in intel_th_gth_probe()
791 		gth->master[i] = -1;  in intel_th_gth_probe()
794 		gth->output[i].gth = gth;  in intel_th_gth_probe()
795 		gth->output[i].index = i;  in intel_th_gth_probe()
796 		gth->output[i].port_type =  in intel_th_gth_probe()
797 			gth_output_parm_get(gth, i, TH_OUTPUT_PARM(port));  in intel_th_gth_probe()
798 		if (gth->output[i].port_type == GTH_NONE)  in intel_th_gth_probe()
801 		ret = intel_th_output_enable(th, gth->output[i].port_type);  in intel_th_gth_probe()
807 	if (intel_th_output_attributes(gth) ||  in intel_th_gth_probe()
808 	    intel_th_master_attributes(gth)) {  in intel_th_gth_probe()
811 		if (gth->output_group.attrs)  in intel_th_gth_probe()
812 			sysfs_remove_group(&gth->dev->kobj, &gth->output_group);  in intel_th_gth_probe()
821 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);  in intel_th_gth_remove()  local
823 	sysfs_remove_group(&gth->dev->kobj, &gth->output_group);  in intel_th_gth_remove()
824 	sysfs_remove_group(&gth->dev->kobj, &gth->master_group);  in intel_th_gth_remove()