Lines Matching refs:coresight_etm4x_reg
2545 #define coresight_etm4x_reg(name, offset) \ macro
2549 coresight_etm4x_reg(trcpdcr, TRCPDCR),
2550 coresight_etm4x_reg(trcpdsr, TRCPDSR),
2551 coresight_etm4x_reg(trclsr, TRCLSR),
2552 coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS),
2553 coresight_etm4x_reg(trcdevid, TRCDEVID),
2554 coresight_etm4x_reg(trcdevtype, TRCDEVTYPE),
2555 coresight_etm4x_reg(trcpidr0, TRCPIDR0),
2556 coresight_etm4x_reg(trcpidr1, TRCPIDR1),
2557 coresight_etm4x_reg(trcpidr2, TRCPIDR2),
2558 coresight_etm4x_reg(trcpidr3, TRCPIDR3),
2559 coresight_etm4x_reg(trcoslsr, TRCOSLSR),
2560 coresight_etm4x_reg(trcconfig, TRCCONFIGR),
2562 coresight_etm4x_reg(trcdevarch, TRCDEVARCH),
2567 coresight_etm4x_reg(trcidr0, TRCIDR0),
2568 coresight_etm4x_reg(trcidr1, TRCIDR1),
2569 coresight_etm4x_reg(trcidr2, TRCIDR2),
2570 coresight_etm4x_reg(trcidr3, TRCIDR3),
2571 coresight_etm4x_reg(trcidr4, TRCIDR4),
2572 coresight_etm4x_reg(trcidr5, TRCIDR5),
2574 coresight_etm4x_reg(trcidr8, TRCIDR8),
2575 coresight_etm4x_reg(trcidr9, TRCIDR9),
2576 coresight_etm4x_reg(trcidr10, TRCIDR10),
2577 coresight_etm4x_reg(trcidr11, TRCIDR11),
2578 coresight_etm4x_reg(trcidr12, TRCIDR12),
2579 coresight_etm4x_reg(trcidr13, TRCIDR13),