Lines Matching +full:tegra194 +full:- +full:gte +full:- +full:lic
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 NVIDIA Corporation
28 #define NV_AON_SLICE_INVALID -1
80 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN)
354 return readl(hte->regs + reg); in tegra_hte_readl()
360 writel(val, hte->regs + reg); in tegra_hte_writel()
370 return -EINVAL; in tegra_hte_map_to_line_id()
372 return -EINVAL; in tegra_hte_map_to_line_id()
393 return -EINVAL; in tegra_hte_line_xlate()
396 if (gc->of_hte_n_cells < 1) in tegra_hte_line_xlate()
397 return -EINVAL; in tegra_hte_line_xlate()
399 if (args->args_count != gc->of_hte_n_cells) in tegra_hte_line_xlate()
400 return -EINVAL; in tegra_hte_line_xlate()
402 desc->attr.line_id = args->args[0]; in tegra_hte_line_xlate()
405 gs = gc->data; in tegra_hte_line_xlate()
406 if (!gs || !gs->prov_data) in tegra_hte_line_xlate()
407 return -EINVAL; in tegra_hte_line_xlate()
412 * 1) The consumer (gpiolib-cdev for example) which uses GPIO global in tegra_hte_line_xlate()
418 * HTE/GTE namespace. in tegra_hte_line_xlate()
420 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { in tegra_hte_line_xlate()
421 line_id = desc->attr.line_id - gs->c->base; in tegra_hte_line_xlate()
422 map = gs->prov_data->map; in tegra_hte_line_xlate()
423 map_sz = gs->prov_data->map_sz; in tegra_hte_line_xlate()
424 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { in tegra_hte_line_xlate()
425 line_id = desc->attr.line_id; in tegra_hte_line_xlate()
426 map = gs->prov_data->sec_map; in tegra_hte_line_xlate()
427 map_sz = gs->prov_data->sec_map_sz; in tegra_hte_line_xlate()
429 line_id = desc->attr.line_id; in tegra_hte_line_xlate()
434 dev_err(gc->dev, "line_id:%u mapping failed\n", in tegra_hte_line_xlate()
435 desc->attr.line_id); in tegra_hte_line_xlate()
439 if (*xlated_id > gc->nlines) in tegra_hte_line_xlate()
440 return -EINVAL; in tegra_hte_line_xlate()
442 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", in tegra_hte_line_xlate()
443 desc->attr.line_id, *xlated_id); in tegra_hte_line_xlate()
462 return -EINVAL; in tegra_hte_en_dis_common()
464 gs = chip->data; in tegra_hte_en_dis_common()
466 if (line_id > chip->nlines) { in tegra_hte_en_dis_common()
467 dev_err(chip->dev, in tegra_hte_en_dis_common()
470 return -EINVAL; in tegra_hte_en_dis_common()
474 line_bit = line_id & (HTE_SLICE_SIZE - 1); in tegra_hte_en_dis_common()
477 spin_lock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
479 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { in tegra_hte_en_dis_common()
480 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
481 dev_dbg(chip->dev, "device suspended"); in tegra_hte_en_dis_common()
482 return -EBUSY; in tegra_hte_en_dis_common()
492 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
494 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", in tegra_hte_en_dis_common()
503 return -EINVAL; in tegra_hte_enable()
511 return -EINVAL; in tegra_hte_disable()
523 if (!chip || !chip->data || !desc) in tegra_hte_request()
524 return -EINVAL; in tegra_hte_request()
526 gs = chip->data; in tegra_hte_request()
527 attr = &desc->attr; in tegra_hte_request()
529 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_request()
530 if (!attr->line_data) in tegra_hte_request()
531 return -EINVAL; in tegra_hte_request()
533 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, in tegra_hte_request()
534 attr->edge_flags); in tegra_hte_request()
538 gs->line_data[line_id].data = attr->line_data; in tegra_hte_request()
539 gs->line_data[line_id].flags = attr->edge_flags; in tegra_hte_request()
552 if (!chip || !chip->data || !desc) in tegra_hte_release()
553 return -EINVAL; in tegra_hte_release()
555 gs = chip->data; in tegra_hte_release()
556 attr = &desc->attr; in tegra_hte_release()
558 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_release()
559 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, in tegra_hte_release()
560 gs->line_data[line_id].flags); in tegra_hte_release()
564 gs->line_data[line_id].data = NULL; in tegra_hte_release()
565 gs->line_data[line_id].flags = 0; in tegra_hte_release()
577 return -EINVAL; in tegra_hte_clk_src_info()
579 ci->hz = HTE_TS_CLK_RATE_HZ; in tegra_hte_clk_src_info()
580 ci->type = CLOCK_MONOTONIC; in tegra_hte_clk_src_info()
589 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_get_level()
590 desc = gs->line_data[line_id].data; in tegra_hte_get_level()
595 return -1; in tegra_hte_get_level()
623 hte_push_ts_ns(gs->chip, line_id, &el); in tegra_hte_read_fifo()
643 struct tegra_hte_soc *hte_dev = chip->data; in tegra_hte_match_from_linedata()
645 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) in tegra_hte_match_from_linedata()
648 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data); in tegra_hte_match_from_linedata()
652 { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte},
653 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
654 { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
655 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
671 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); in tegra_gte_disable()
678 return !strcmp(chip->label, data); in tegra_get_gpiochip_from_name()
683 return chip->fwnode == of_node_to_fwnode(data); in tegra_gpiochip_match()
696 dev = &pdev->dev; in tegra_hte_probe()
700 return -ENOMEM; in tegra_hte_probe()
704 return -ENOMEM; in tegra_hte_probe()
706 dev_set_drvdata(&pdev->dev, hte_dev); in tegra_hte_probe()
707 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); in tegra_hte_probe()
709 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); in tegra_hte_probe()
711 slices = hte_dev->prov_data->slices; in tegra_hte_probe()
716 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_hte_probe()
717 if (IS_ERR(hte_dev->regs)) in tegra_hte_probe()
718 return PTR_ERR(hte_dev->regs); in tegra_hte_probe()
720 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", in tegra_hte_probe()
721 &hte_dev->itr_thrshld); in tegra_hte_probe()
723 hte_dev->itr_thrshld = 1; in tegra_hte_probe()
725 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), in tegra_hte_probe()
727 if (!hte_dev->sl) in tegra_hte_probe()
728 return -ENOMEM; in tegra_hte_probe()
735 hte_dev->hte_irq = ret; in tegra_hte_probe()
736 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, in tegra_hte_probe()
743 gc->nlines = nlines; in tegra_hte_probe()
744 gc->ops = &g_ops; in tegra_hte_probe()
745 gc->dev = dev; in tegra_hte_probe()
746 gc->data = hte_dev; in tegra_hte_probe()
747 gc->xlate_of = tegra_hte_line_xlate; in tegra_hte_probe()
748 gc->xlate_plat = tegra_hte_line_xlate_plat; in tegra_hte_probe()
749 gc->of_hte_n_cells = 1; in tegra_hte_probe()
751 if (hte_dev->prov_data && in tegra_hte_probe()
752 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_probe()
753 hte_dev->line_data = devm_kcalloc(dev, nlines, in tegra_hte_probe()
754 sizeof(*hte_dev->line_data), in tegra_hte_probe()
756 if (!hte_dev->line_data) in tegra_hte_probe()
757 return -ENOMEM; in tegra_hte_probe()
759 gc->match_from_linedata = tegra_hte_match_from_linedata; in tegra_hte_probe()
761 if (of_device_is_compatible(dev->of_node, in tegra_hte_probe()
762 "nvidia,tegra194-gte-aon")) { in tegra_hte_probe()
763 hte_dev->c = gpiochip_find("tegra194-gpio-aon", in tegra_hte_probe()
766 gpio_ctrl = of_parse_phandle(dev->of_node, in tegra_hte_probe()
767 "nvidia,gpio-controller", in tegra_hte_probe()
772 return -ENODEV; in tegra_hte_probe()
775 hte_dev->c = gpiochip_find(gpio_ctrl, in tegra_hte_probe()
780 if (!hte_dev->c) in tegra_hte_probe()
781 return dev_err_probe(dev, -EPROBE_DEFER, in tegra_hte_probe()
785 hte_dev->chip = gc; in tegra_hte_probe()
787 ret = devm_hte_register_chip(hte_dev->chip); in tegra_hte_probe()
789 dev_err(gc->dev, "hte chip register failed"); in tegra_hte_probe()
794 hte_dev->sl[i].flags = 0; in tegra_hte_probe()
795 spin_lock_init(&hte_dev->sl[i].s_lock); in tegra_hte_probe()
800 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); in tegra_hte_probe()
803 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); in tegra_hte_probe()
807 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); in tegra_hte_probe()
816 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_resume_early()
819 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); in tegra_hte_resume_early()
822 spin_lock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
825 gs->sl[i].r_val); in tegra_hte_resume_early()
826 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_resume_early()
827 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
837 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_suspend_late()
840 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); in tegra_hte_suspend_late()
842 spin_lock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()
843 gs->sl[i].r_val = tegra_hte_readl(gs, in tegra_hte_suspend_late()
845 set_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_suspend_late()
846 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()