1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
27 #include <asm/dma-iommu.h>
47 	writel(v, host1x->common_regs + r);  in host1x_common_writel()
52 	writel(v, host1x->hv_regs + r);  in host1x_hypervisor_writel()
57 	return readl(host1x->hv_regs + r);  in host1x_hypervisor_readl()
62 	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;  in host1x_sync_writel()
69 	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;  in host1x_sync_readl()
76 	writel(v, ch->regs + r);  in host1x_ch_writel()
81 	return readl(ch->regs + r);  in host1x_ch_readl()
263 	{ .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
264 	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
265 	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
266 	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
267 	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
268 	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
269 	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
270 	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
277 	const struct host1x_info *info = host->info;  in host1x_setup_virtualization_tables()
280 	if (!info->has_hypervisor)  in host1x_setup_virtualization_tables()
283 	for (i = 0; i < info->num_sid_entries; i++) {  in host1x_setup_virtualization_tables()
284 		const struct host1x_sid_entry *entry = &info->sid_table[i];  in host1x_setup_virtualization_tables()
286 		host1x_hypervisor_writel(host, entry->offset, entry->base);  in host1x_setup_virtualization_tables()
287 		host1x_hypervisor_writel(host, entry->limit, entry->base + 4);  in host1x_setup_virtualization_tables()
290 	for (i = 0; i < info->streamid_vm_table.count; i++) {  in host1x_setup_virtualization_tables()
292 		host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);  in host1x_setup_virtualization_tables()
295 	for (i = 0; i < info->classid_vm_table.count; i++) {  in host1x_setup_virtualization_tables()
297 		host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);  in host1x_setup_virtualization_tables()
300 	for (i = 0; i < info->mmio_vm_table.count; i++) {  in host1x_setup_virtualization_tables()
302 		host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);  in host1x_setup_virtualization_tables()
321 	 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can  in host1x_wants_iommu()
329 	 * buffers will be mapped into a 32-bit IOVA space that host1x can  in host1x_wants_iommu()
337 	if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {  in host1x_wants_iommu()
347 	struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);  in host1x_iommu_attach()
351 	if (host->dev->archdata.mapping) {  in host1x_iommu_attach()
353 				to_dma_iommu_mapping(host->dev);  in host1x_iommu_attach()
354 		arm_iommu_detach_device(host->dev);  in host1x_iommu_attach()
357 		domain = iommu_get_domain_for_dev(host->dev);  in host1x_iommu_attach()
372 	host->group = iommu_group_get(host->dev);  in host1x_iommu_attach()
373 	if (host->group) {  in host1x_iommu_attach()
382 		host->domain = iommu_domain_alloc(&platform_bus_type);  in host1x_iommu_attach()
383 		if (!host->domain) {  in host1x_iommu_attach()
384 			err = -ENOMEM;  in host1x_iommu_attach()
388 		err = iommu_attach_group(host->domain, host->group);  in host1x_iommu_attach()
390 			if (err == -ENODEV)  in host1x_iommu_attach()
396 		geometry = &host->domain->geometry;  in host1x_iommu_attach()
397 		start = geometry->aperture_start & host->info->dma_mask;  in host1x_iommu_attach()
398 		end = geometry->aperture_end & host->info->dma_mask;  in host1x_iommu_attach()
400 		order = __ffs(host->domain->pgsize_bitmap);  in host1x_iommu_attach()
401 		init_iova_domain(&host->iova, 1UL << order, start >> order);  in host1x_iommu_attach()
402 		host->iova_end = end;  in host1x_iommu_attach()
404 		domain = host->domain;  in host1x_iommu_attach()
410 	iommu_domain_free(host->domain);  in host1x_iommu_attach()
411 	host->domain = NULL;  in host1x_iommu_attach()
415 	iommu_group_put(host->group);  in host1x_iommu_attach()
416 	host->group = NULL;  in host1x_iommu_attach()
423 	u64 mask = host->info->dma_mask;  in host1x_iommu_init()
430 		dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);  in host1x_iommu_init()
439 	 * Newer generations of Tegra (Tegra186 and later) support a wide  in host1x_iommu_init()
442 	if (!domain && !host->info->has_wide_gather)  in host1x_iommu_init()
445 	err = dma_coerce_mask_and_coherent(host->dev, mask);  in host1x_iommu_init()
447 		dev_err(host->dev, "failed to set DMA mask: %d\n", err);  in host1x_iommu_init()
456 	if (host->domain) {  in host1x_iommu_exit()
457 		put_iova_domain(&host->iova);  in host1x_iommu_exit()
458 		iommu_detach_group(host->domain, host->group);  in host1x_iommu_exit()
460 		iommu_domain_free(host->domain);  in host1x_iommu_exit()
461 		host->domain = NULL;  in host1x_iommu_exit()
465 		iommu_group_put(host->group);  in host1x_iommu_exit()
466 		host->group = NULL;  in host1x_iommu_exit()
474 	host->resets[0].id = "mc";  in host1x_get_resets()
475 	host->resets[1].id = "host1x";  in host1x_get_resets()
476 	host->nresets = ARRAY_SIZE(host->resets);  in host1x_get_resets()
479 				host->dev, host->nresets, host->resets);  in host1x_get_resets()
481 		dev_err(host->dev, "failed to get reset: %d\n", err);  in host1x_get_resets()
493 	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);  in host1x_probe()
495 		return -ENOMEM;  in host1x_probe()
497 	host->info = of_device_get_match_data(&pdev->dev);  in host1x_probe()
499 	if (host->info->has_hypervisor) {  in host1x_probe()
500 		host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");  in host1x_probe()
501 		if (IS_ERR(host->regs))  in host1x_probe()
502 			return PTR_ERR(host->regs);  in host1x_probe()
504 		host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");  in host1x_probe()
505 		if (IS_ERR(host->hv_regs))  in host1x_probe()
506 			return PTR_ERR(host->hv_regs);  in host1x_probe()
508 		if (host->info->has_common) {  in host1x_probe()
509 			host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");  in host1x_probe()
510 			if (IS_ERR(host->common_regs))  in host1x_probe()
511 				return PTR_ERR(host->common_regs);  in host1x_probe()
514 		host->regs = devm_platform_ioremap_resource(pdev, 0);  in host1x_probe()
515 		if (IS_ERR(host->regs))  in host1x_probe()
516 			return PTR_ERR(host->regs);  in host1x_probe()
519 	host->syncpt_irq = platform_get_irq(pdev, 0);  in host1x_probe()
520 	if (host->syncpt_irq < 0)  in host1x_probe()
521 		return host->syncpt_irq;  in host1x_probe()
523 	mutex_init(&host->devices_lock);  in host1x_probe()
524 	INIT_LIST_HEAD(&host->devices);  in host1x_probe()
525 	INIT_LIST_HEAD(&host->list);  in host1x_probe()
526 	host->dev = &pdev->dev;  in host1x_probe()
531 	host->dev->dma_parms = &host->dma_parms;  in host1x_probe()
532 	dma_set_max_seg_size(host->dev, UINT_MAX);  in host1x_probe()
534 	if (host->info->init) {  in host1x_probe()
535 		err = host->info->init(host);  in host1x_probe()
540 	host->clk = devm_clk_get(&pdev->dev, NULL);  in host1x_probe()
541 	if (IS_ERR(host->clk)) {  in host1x_probe()
542 		err = PTR_ERR(host->clk);  in host1x_probe()
544 		if (err != -EPROBE_DEFER)  in host1x_probe()
545 			dev_err(&pdev->dev, "failed to get clock: %d\n", err);  in host1x_probe()
554 	host1x_bo_cache_init(&host->cache);  in host1x_probe()
558 		dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);  in host1x_probe()
562 	err = host1x_channel_list_init(&host->channel_list,  in host1x_probe()
563 				       host->info->nb_channels);  in host1x_probe()
565 		dev_err(&pdev->dev, "failed to initialize channel list\n");  in host1x_probe()
571 		dev_err(&pdev->dev, "failed to initialize context list\n");  in host1x_probe()
577 		dev_err(&pdev->dev, "failed to initialize syncpts\n");  in host1x_probe()
583 		dev_err(&pdev->dev, "failed to initialize interrupts\n");  in host1x_probe()
587 	pm_runtime_enable(&pdev->dev);  in host1x_probe()
589 	err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);  in host1x_probe()
594 	err = pm_runtime_resume_and_get(&pdev->dev);  in host1x_probe()
604 	err = devm_of_platform_populate(&pdev->dev);  in host1x_probe()
615 	pm_runtime_put_sync_suspend(&pdev->dev);  in host1x_probe()
617 	pm_runtime_disable(&pdev->dev);  in host1x_probe()
623 	host1x_memory_context_list_free(&host->context_list);  in host1x_probe()
625 	host1x_channel_list_free(&host->channel_list);  in host1x_probe()
629 	host1x_bo_cache_destroy(&host->cache);  in host1x_probe()
641 	pm_runtime_force_suspend(&pdev->dev);  in host1x_remove()
645 	host1x_memory_context_list_free(&host->context_list);  in host1x_remove()
646 	host1x_channel_list_free(&host->channel_list);  in host1x_remove()
648 	host1x_bo_cache_destroy(&host->cache);  in host1x_remove()
661 	err = reset_control_bulk_assert(host->nresets, host->resets);  in host1x_runtime_suspend()
669 	clk_disable_unprepare(host->clk);  in host1x_runtime_suspend()
670 	reset_control_bulk_release(host->nresets, host->resets);  in host1x_runtime_suspend()
687 	err = reset_control_bulk_acquire(host->nresets, host->resets);  in host1x_runtime_resume()
693 	err = clk_prepare_enable(host->clk);  in host1x_runtime_resume()
699 	err = reset_control_bulk_deassert(host->nresets, host->resets);  in host1x_runtime_resume()
712 	clk_disable_unprepare(host->clk);  in host1x_runtime_resume()
714 	reset_control_bulk_release(host->nresets, host->resets);  in host1x_runtime_resume()
722 	/* TODO: add system suspend-resume once driver will be ready for that */
727 		.name = "tegra-host1x",
764  * host1x_get_dma_mask() - query the supported DMA mask for host1x
772 	return host1x->info->dma_mask;  in host1x_get_dma_mask()
776 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");