128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,  in vc4_hdmi_mode_needs_scrambling()  argument
151 	unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);  in vc4_hdmi_mode_needs_scrambling()
159 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_is_full_range()  local
168 		drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;  in vc4_hdmi_is_full_range()
525 		const struct drm_display_mode *mode;  in vc4_hdmi_connector_get_modes()  local
527 		list_for_each_entry(mode, &connector->probed_modes, head) {  in vc4_hdmi_connector_get_modes()
528 			if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {  in vc4_hdmi_connector_get_modes()
910 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_set_avi_infoframe()  local
917 						       connector, mode);  in vc4_hdmi_set_avi_infoframe()
924 					   connector, mode,  in vc4_hdmi_set_avi_infoframe()
1009 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_enable_scrambling()  local
1018 	if (!vc4_hdmi_mode_needs_scrambling(mode,  in vc4_hdmi_enable_scrambling()
1166 			       const struct drm_display_mode *mode)  in vc4_hdmi_csc_setup()  argument
1403 			       const struct drm_display_mode *mode)  in vc5_hdmi_csc_setup()  argument
1469 				 const struct drm_display_mode *mode)  in vc4_hdmi_set_timings()  argument
1472 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;  in vc4_hdmi_set_timings()
1473 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;  in vc4_hdmi_set_timings()
1474 	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;  in vc4_hdmi_set_timings()
1475 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;  in vc4_hdmi_set_timings()
1476 	u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,  in vc4_hdmi_set_timings()
1478 		     VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,  in vc4_hdmi_set_timings()
1480 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));  in vc4_hdmi_set_timings()
1482 		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +  in vc4_hdmi_set_timings()
1486 			  VC4_SET_FIELD(mode->crtc_vtotal -  in vc4_hdmi_set_timings()
1487 					mode->crtc_vsync_end,  in vc4_hdmi_set_timings()
1501 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep,  in vc4_hdmi_set_timings()
1505 		   VC4_SET_FIELD((mode->htotal -  in vc4_hdmi_set_timings()
1506 				  mode->hsync_end) * pixel_rep,  in vc4_hdmi_set_timings()
1508 		   VC4_SET_FIELD((mode->hsync_end -  in vc4_hdmi_set_timings()
1509 				  mode->hsync_start) * pixel_rep,  in vc4_hdmi_set_timings()
1511 		   VC4_SET_FIELD((mode->hsync_start -  in vc4_hdmi_set_timings()
1512 				  mode->hdisplay) * pixel_rep,  in vc4_hdmi_set_timings()
1533 				 const struct drm_display_mode *mode)  in vc5_hdmi_set_timings()  argument
1538 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;  in vc5_hdmi_set_timings()
1539 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;  in vc5_hdmi_set_timings()
1540 	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;  in vc5_hdmi_set_timings()
1541 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;  in vc5_hdmi_set_timings()
1542 	u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,  in vc5_hdmi_set_timings()
1544 		     VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,  in vc5_hdmi_set_timings()
1546 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));  in vc5_hdmi_set_timings()
1547 	u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),  in vc5_hdmi_set_timings()
1549 		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +  in vc5_hdmi_set_timings()
1553 			  VC4_SET_FIELD(mode->crtc_vtotal -  in vc5_hdmi_set_timings()
1554 					mode->crtc_vsync_end,  in vc5_hdmi_set_timings()
1569 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep,  in vc5_hdmi_set_timings()
1571 		   VC4_SET_FIELD((mode->hsync_start -  in vc5_hdmi_set_timings()
1572 				  mode->hdisplay) * pixel_rep,  in vc5_hdmi_set_timings()
1576 		   VC4_SET_FIELD((mode->htotal -  in vc5_hdmi_set_timings()
1577 				  mode->hsync_end) * pixel_rep,  in vc5_hdmi_set_timings()
1579 		   VC4_SET_FIELD((mode->hsync_end -  in vc5_hdmi_set_timings()
1580 				  mode->hsync_start) * pixel_rep,  in vc5_hdmi_set_timings()
1692 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_encoder_pre_crtc_configure()  local
1782 		vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);  in vc4_hdmi_encoder_pre_crtc_configure()
1807 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_encoder_pre_crtc_enable()  local
1819 		vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);  in vc4_hdmi_encoder_pre_crtc_enable()
1836 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_encoder_post_crtc_enable()  local
1838 	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;  in vc4_hdmi_encoder_post_crtc_enable()
1839 	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;  in vc4_hdmi_encoder_post_crtc_enable()
1932 				  const struct drm_display_mode *mode,  in vc4_hdmi_sink_supports_format_bpc()  argument
1936 	u8 vic = drm_match_cea_mode(mode);  in vc4_hdmi_sink_supports_format_bpc()
2015 			     const struct drm_display_mode *mode,  in vc4_hdmi_encoder_clock_valid()  argument
2030 	    mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&  in vc4_hdmi_encoder_clock_valid()
2031 	    drm_mode_vrefresh(mode) >= 50)  in vc4_hdmi_encoder_clock_valid()
2041 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,  in vc4_hdmi_encoder_compute_mode_clock()  argument
2045 	unsigned long long clock = mode->clock * 1000ULL;  in vc4_hdmi_encoder_compute_mode_clock()
2047 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)  in vc4_hdmi_encoder_compute_mode_clock()
2062 			       const struct drm_display_mode *mode,  in vc4_hdmi_encoder_compute_clock()  argument
2067 	clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);  in vc4_hdmi_encoder_compute_clock()
2068 	if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)  in vc4_hdmi_encoder_compute_clock()
2079 				const struct drm_display_mode *mode,  in vc4_hdmi_encoder_compute_format()  argument
2090 	if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {  in vc4_hdmi_encoder_compute_format()
2094 						     mode, bpc, format);  in vc4_hdmi_encoder_compute_format()
2104 	if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {  in vc4_hdmi_encoder_compute_format()
2108 						     mode, bpc, format);  in vc4_hdmi_encoder_compute_format()
2123 				const struct drm_display_mode *mode)  in vc4_hdmi_encoder_compute_config()  argument
2135 						      mode, bpc);  in vc4_hdmi_encoder_compute_config()
2143 			mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),  in vc4_hdmi_encoder_compute_config()
2168 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;  in vc4_hdmi_encoder_atomic_check()  local
2169 	unsigned long long tmds_char_rate = mode->clock * 1000;  in vc4_hdmi_encoder_atomic_check()
2174 		if (mode->flags & DRM_MODE_FLAG_DBLCLK) {  in vc4_hdmi_encoder_atomic_check()
2181 			if ((mode->hsync_start - mode->hdisplay) & 1)  in vc4_hdmi_encoder_atomic_check()
2182 				mode->hsync_start--;  in vc4_hdmi_encoder_atomic_check()
2183 			if ((mode->hsync_end - mode->hsync_start) & 1)  in vc4_hdmi_encoder_atomic_check()
2184 				mode->hsync_end--;  in vc4_hdmi_encoder_atomic_check()
2188 		if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||  in vc4_hdmi_encoder_atomic_check()
2189 		    (mode->hsync_end % 2) || (mode->htotal % 2))  in vc4_hdmi_encoder_atomic_check()
2203 		mode->clock = 238560;  in vc4_hdmi_encoder_atomic_check()
2204 		tmds_char_rate = mode->clock * 1000;  in vc4_hdmi_encoder_atomic_check()
2207 	ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);  in vc4_hdmi_encoder_atomic_check()
2221 			    const struct drm_display_mode *mode)  in vc4_hdmi_encoder_mode_valid()  argument
2226 	    !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&  in vc4_hdmi_encoder_mode_valid()
2227 	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||  in vc4_hdmi_encoder_mode_valid()
2228 	     (mode->hsync_end % 2) || (mode->htotal % 2)))  in vc4_hdmi_encoder_mode_valid()
2231 	return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);  in vc4_hdmi_encoder_mode_valid()
2331 	const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;  in vc4_hdmi_set_n_cts()  local
2339 	tmp = (u64)(mode->clock * 1000) * n;  in vc4_hdmi_set_n_cts()