Lines Matching +full:timeout +full:- +full:lp1 +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
616 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
625 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
629 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
631 tx = chan->device->device_prep_dma_memcpy(chan, in dsi_dma_workaround_write()
632 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
633 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
640 cookie = tx->tx_submit(tx); in dsi_dma_workaround_write()
654 readl(dsi->regs + (offset)); \
659 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
661 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
662 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
729 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
732 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
733 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
734 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
737 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
738 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
739 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
742 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
743 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
744 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
756 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
757 "Timeout waiting for DSI ULPS entry: STAT 0x%08x", in vc4_dsi_ulps()
775 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
776 "Timeout waiting for DSI STOP entry: STAT 0x%08x", in vc4_dsi_ulps()
816 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_post_disable()
818 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_bridge_post_disable()
819 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_bridge_post_disable()
820 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_bridge_post_disable()
825 /* Extends the mode's blank intervals to handle BCM2835's integer-only
835 * higher-than-expected clock rate to the panel, but that's what the
843 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_bridge_mode_fixup()
845 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_bridge_mode_fixup()
846 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_bridge_mode_fixup()
861 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_bridge_mode_fixup()
863 adjusted_mode->clock = pixel_clock_hz / 1000; in vc4_dsi_bridge_mode_fixup()
866 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / in vc4_dsi_bridge_mode_fixup()
867 mode->clock; in vc4_dsi_bridge_mode_fixup()
868 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; in vc4_dsi_bridge_mode_fixup()
869 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; in vc4_dsi_bridge_mode_fixup()
877 struct drm_atomic_state *state = old_state->base.state; in vc4_dsi_bridge_pre_enable()
880 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_pre_enable()
896 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_bridge_pre_enable()
901 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_pre_enable()
902 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_bridge_pre_enable()
903 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_pre_enable()
911 bridge->encoder); in vc4_dsi_bridge_pre_enable()
912 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; in vc4_dsi_bridge_pre_enable()
914 mode = &crtc_state->adjusted_mode; in vc4_dsi_bridge_pre_enable()
916 pixel_clock_hz = mode->clock * 1000; in vc4_dsi_bridge_pre_enable()
922 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_bridge_pre_enable()
923 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_bridge_pre_enable()
925 dev_err(&dsi->pdev->dev, in vc4_dsi_bridge_pre_enable()
942 if (dsi->variant->port == 0) { in vc4_dsi_bridge_pre_enable()
946 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
949 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_bridge_pre_enable()
970 if (dsi->lanes < 4) in vc4_dsi_bridge_pre_enable()
972 if (dsi->lanes < 3) in vc4_dsi_bridge_pre_enable()
974 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
987 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_bridge_pre_enable()
993 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
999 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
1009 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_bridge_pre_enable()
1015 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_bridge_pre_enable()
1060 /* T_INIT is how long STOP is driven after power-up to in vc4_dsi_bridge_pre_enable()
1061 * indicate to the slave (also coming out of power-up) that in vc4_dsi_bridge_pre_enable()
1064 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and in vc4_dsi_bridge_pre_enable()
1067 * conservative 5ms, and we maintain that here. in vc4_dsi_bridge_pre_enable()
1085 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1086 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1087 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1089 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_bridge_pre_enable()
1091 (dsi->variant->port == 0 ? in vc4_dsi_bridge_pre_enable()
1092 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : in vc4_dsi_bridge_pre_enable()
1093 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); in vc4_dsi_bridge_pre_enable()
1099 /* HS timeout in HS clock cycles: disabled. */ in vc4_dsi_bridge_pre_enable()
1101 /* LP receive timeout in HS clocks. */ in vc4_dsi_bridge_pre_enable()
1103 /* Bus turnaround timeout */ in vc4_dsi_bridge_pre_enable()
1105 /* Display reset sequence timeout */ in vc4_dsi_bridge_pre_enable()
1117 if (dsi->variant->port == 0) in vc4_dsi_bridge_pre_enable()
1129 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_bridge_pre_enable()
1131 VC4_SET_FIELD(dsi->divider, in vc4_dsi_bridge_pre_enable()
1133 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_bridge_pre_enable()
1155 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_enable()
1156 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_bridge_enable()
1157 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_enable()
1167 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, in vc4_dsi_bridge_attach()
1168 &dsi->bridge, flags); in vc4_dsi_bridge_attach()
1178 bool is_long = mipi_dsi_packet_format_is_long(msg->type); in vc4_dsi_host_transfer()
1189 * The command FIFO takes byte-oriented data, but is of in vc4_dsi_host_transfer()
1203 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / in vc4_dsi_host_transfer()
1212 if (msg->rx_len) { in vc4_dsi_host_transfer()
1232 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in vc4_dsi_host_transfer()
1252 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1253 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1254 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1257 if (msg->rx_len) { in vc4_dsi_host_transfer()
1269 if (msg->rx_len) { in vc4_dsi_host_transfer()
1282 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1284 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1285 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1287 ret = -ETIMEDOUT; in vc4_dsi_host_transfer()
1289 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1297 if (ret == 0 && msg->rx_len) { in vc4_dsi_host_transfer()
1299 u8 *msg_rx = msg->rx_buf; in vc4_dsi_host_transfer()
1305 if (rxlen != msg->rx_len) { in vc4_dsi_host_transfer()
1307 rxlen, (int)msg->rx_len); in vc4_dsi_host_transfer()
1308 ret = -ENXIO; in vc4_dsi_host_transfer()
1312 for (i = 0; i < msg->rx_len; i++) in vc4_dsi_host_transfer()
1319 if (msg->rx_len > 1) { in vc4_dsi_host_transfer()
1349 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1350 dsi->channel = device->channel; in vc4_dsi_host_attach()
1351 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1353 switch (device->format) { in vc4_dsi_host_attach()
1355 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1356 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1359 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1360 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1363 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1364 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1367 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1368 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1371 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1372 dsi->format); in vc4_dsi_host_attach()
1376 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1377 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1382 drm_bridge_add(&dsi->bridge); in vc4_dsi_host_attach()
1384 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1386 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_attach()
1398 component_del(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_detach()
1399 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_detach()
1423 struct drm_device *drm = encoder->dev; in vc4_dsi_late_register()
1426 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); in vc4_dsi_late_register()
1458 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1459 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1460 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1471 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); in dsi_handle_error()
1511 DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention"); in vc4_dsi_irq_handler()
1513 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout"); in vc4_dsi_irq_handler()
1515 DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout"); in vc4_dsi_irq_handler()
1517 DSI_PORT_BIT(INT_TA_TO), "turnaround timeout"); in vc4_dsi_irq_handler()
1519 DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout"); in vc4_dsi_irq_handler()
1521 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1524 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1527 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1528 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1536 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1537 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1543 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1544 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1555 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1556 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1560 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1561 return -ENOMEM; in vc4_dsi_init_phy_clocks()
1562 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1565 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1571 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1582 fix->mult = 1; in vc4_dsi_init_phy_clocks()
1583 fix->div = phy_clocks[i].div; in vc4_dsi_init_phy_clocks()
1584 fix->hw.init = &init; in vc4_dsi_init_phy_clocks()
1592 ret = devm_clk_hw_register(dev, &fix->hw); in vc4_dsi_init_phy_clocks()
1596 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1599 return of_clk_add_hw_provider(dev->of_node, in vc4_dsi_init_phy_clocks()
1601 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1607 struct device *dev = &dsi->pdev->dev; in vc4_dsi_dma_mem_release()
1609 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); in vc4_dsi_dma_mem_release()
1610 dsi->reg_dma_mem = NULL; in vc4_dsi_dma_mem_release()
1617 dma_release_channel(dsi->reg_dma_chan); in vc4_dsi_dma_chan_release()
1618 dsi->reg_dma_chan = NULL; in vc4_dsi_dma_chan_release()
1631 kref_get(&dsi->kref); in vc4_dsi_get()
1636 kref_put(&dsi->kref, &vc4_dsi_release); in vc4_dsi_put()
1651 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_bind()
1660 dsi->variant = of_device_get_match_data(dev); in vc4_dsi_bind()
1662 dsi->encoder.type = dsi->variant->port ? in vc4_dsi_bind()
1665 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1666 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1667 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1669 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1670 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1671 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1676 return -ENODEV; in vc4_dsi_bind()
1683 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1686 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1687 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1689 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1691 return -ENOMEM; in vc4_dsi_bind()
1701 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1702 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1703 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1704 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1718 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1722 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1723 /* At startup enable error-reporting interrupts and nothing else. */ in vc4_dsi_bind()
1728 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1738 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1743 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1744 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1745 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1746 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1751 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1752 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1753 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1754 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1759 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1760 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1761 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1762 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1767 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); in vc4_dsi_bind()
1768 if (IS_ERR(dsi->out_bridge)) in vc4_dsi_bind()
1769 return PTR_ERR(dsi->out_bridge); in vc4_dsi_bind()
1772 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1793 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); in vc4_dsi_bind()
1806 struct device *dev = &pdev->dev; in vc4_dsi_dev_probe()
1811 return -ENOMEM; in vc4_dsi_dev_probe()
1814 kref_init(&dsi->kref); in vc4_dsi_dev_probe()
1816 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1817 dsi->bridge.funcs = &vc4_dsi_bridge_funcs; in vc4_dsi_dev_probe()
1819 dsi->bridge.of_node = dev->of_node; in vc4_dsi_dev_probe()
1821 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; in vc4_dsi_dev_probe()
1822 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1823 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1824 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1831 struct device *dev = &pdev->dev; in vc4_dsi_dev_remove()
1834 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()