Lines Matching +full:bcm2835 +full:- +full:dpi
1 // SPDX-License-Identifier: GPL-2.0-only
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
27 * output-specific clock. Since the encoders also directly consume
57 writel(val, vc4_crtc->regs + (offset)); \
63 readl(vc4_crtc->regs + (offset)); \
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation()
87 /* Top/base are supposed to be 4-pixel aligned, but the in vc4_crtc_get_cob_allocation()
94 return top - base + 4; in vc4_crtc_get_cob_allocation()
103 struct drm_device *dev = crtc->dev; in vc4_crtc_get_scanout_position()
105 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position()
107 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_get_scanout_position()
124 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); in vc4_crtc_get_scanout_position()
136 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in vc4_crtc_get_scanout_position()
140 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2) in vc4_crtc_get_scanout_position()
141 *hpos += mode->crtc_htotal / 2; in vc4_crtc_get_scanout_position()
144 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel); in vc4_crtc_get_scanout_position()
145 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
146 fifo_lines = cob_size / mode->crtc_hdisplay; in vc4_crtc_get_scanout_position()
161 * incrementing vpos. Therefore we choose HVS read position - in vc4_crtc_get_scanout_position()
165 *vpos -= fifo_lines + 1; in vc4_crtc_get_scanout_position()
173 * fifo with new lines from the top-most lines of the new framebuffers. in vc4_crtc_get_scanout_position()
179 vblank_lines = mode->vtotal - mode->vdisplay; in vc4_crtc_get_scanout_position()
191 *vpos = -vblank_lines; in vc4_crtc_get_scanout_position()
194 *stime = vc4_crtc->t_vblank; in vc4_crtc_get_scanout_position()
196 *etime = vc4_crtc->t_vblank; in vc4_crtc_get_scanout_position()
224 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); in vc4_get_fifo_full_level()
225 u32 fifo_len_bytes = pv_data->fifo_depth; in vc4_get_fifo_full_level()
240 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; in vc4_get_fifo_full_level()
242 return fifo_len_bytes - 14; in vc4_get_fifo_full_level()
250 if (crtc_data->hvs_output == 5) in vc4_get_fifo_full_level()
266 if (!vc4->is_vc5) in vc4_get_fifo_full_level()
267 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; in vc4_get_fifo_full_level()
269 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; in vc4_get_fifo_full_level()
298 WARN_ON(hweight32(state->encoder_mask) > 1); in vc4_get_crtc_encoder()
300 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) in vc4_get_crtc_encoder()
309 struct drm_device *dev = crtc->dev; in vc4_crtc_pixelvalve_reset()
325 struct drm_device *dev = crtc->dev; in vc4_crtc_config_pv()
330 struct drm_crtc_state *crtc_state = crtc->state; in vc4_crtc_config_pv()
331 struct drm_display_mode *mode = &crtc_state->adjusted_mode; in vc4_crtc_config_pv()
332 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; in vc4_crtc_config_pv()
333 bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 || in vc4_crtc_config_pv()
334 vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1; in vc4_crtc_config_pv()
335 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1; in vc4_crtc_config_pv()
336 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || in vc4_crtc_config_pv()
337 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); in vc4_crtc_config_pv()
338 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1; in vc4_crtc_config_pv()
339 bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC; in vc4_crtc_config_pv()
341 u8 ppc = pv_data->pixels_per_clock; in vc4_crtc_config_pv()
343 u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end; in vc4_crtc_config_pv()
344 u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start; in vc4_crtc_config_pv()
345 u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay; in vc4_crtc_config_pv()
354 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); in vc4_crtc_config_pv()
355 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", in vc4_crtc_config_pv()
357 drm_print_regset32(&p, &vc4_crtc->regset); in vc4_crtc_config_pv()
363 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
365 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
369 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
371 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
376 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc); in vc4_crtc_config_pv()
383 if (mode->htotal == 858) { in vc4_crtc_config_pv()
384 /* 525-line mode (NTSC or PAL-M) */ in vc4_crtc_config_pv()
399 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
426 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
429 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); in vc4_crtc_config_pv()
431 if (vc4->is_vc5) in vc4_crtc_config_pv()
439 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
443 VC4_SET_FIELD(vc4_encoder->clock_select, in vc4_crtc_config_pv()
447 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); in vc4_crtc_config_pv()
448 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", in vc4_crtc_config_pv()
450 drm_print_regset32(&p, &vc4_crtc->regset); in vc4_crtc_config_pv()
459 struct vc4_hvs *hvs = vc4->hvs; in require_hvs_enabled()
472 struct drm_device *dev = crtc->dev; in vc4_crtc_disable()
477 return -ENODEV; in vc4_crtc_disable()
502 if (vc4_encoder && vc4_encoder->post_crtc_disable) in vc4_crtc_disable()
503 vc4_encoder->post_crtc_disable(encoder, state); in vc4_crtc_disable()
506 vc4_hvs_stop_channel(vc4->hvs, channel); in vc4_crtc_disable()
508 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) in vc4_crtc_disable()
509 vc4_encoder->post_crtc_powerdown(encoder, state); in vc4_crtc_disable()
518 struct drm_device *drm = crtc->dev; in vc4_crtc_disable_at_boot()
529 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, in vc4_crtc_disable_at_boot()
530 "brcm,bcm2711-pixelvalve2") || in vc4_crtc_disable_at_boot()
531 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, in vc4_crtc_disable_at_boot()
532 "brcm,bcm2711-pixelvalve4"))) in vc4_crtc_disable_at_boot()
541 channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output); in vc4_crtc_disable_at_boot()
550 encoder_type = pv_data->encoder_types[encoder_sel]; in vc4_crtc_disable_at_boot()
556 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); in vc4_crtc_disable_at_boot()
575 struct drm_device *dev = crtc->dev; in vc4_crtc_send_vblank()
578 if (!crtc->state || !crtc->state->event) in vc4_crtc_send_vblank()
581 spin_lock_irqsave(&dev->event_lock, flags); in vc4_crtc_send_vblank()
582 drm_crtc_send_vblank_event(crtc, crtc->state->event); in vc4_crtc_send_vblank()
583 crtc->state->event = NULL; in vc4_crtc_send_vblank()
584 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_crtc_send_vblank()
594 struct drm_device *dev = crtc->dev; in vc4_crtc_atomic_disable()
597 crtc->name, crtc->base.id, encoder->name, encoder->base.id); in vc4_crtc_atomic_disable()
604 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel); in vc4_crtc_atomic_disable()
618 struct drm_device *dev = crtc->dev; in vc4_crtc_atomic_enable()
625 crtc->name, crtc->base.id, encoder->name, encoder->base.id); in vc4_crtc_atomic_enable()
639 if (vc4_encoder->pre_crtc_configure) in vc4_crtc_atomic_enable()
640 vc4_encoder->pre_crtc_configure(encoder, state); in vc4_crtc_atomic_enable()
646 if (vc4_encoder->pre_crtc_enable) in vc4_crtc_atomic_enable()
647 vc4_encoder->pre_crtc_enable(encoder, state); in vc4_crtc_atomic_enable()
655 if (vc4_encoder->post_crtc_enable) in vc4_crtc_atomic_enable()
656 vc4_encoder->post_crtc_enable(encoder, state); in vc4_crtc_atomic_enable()
665 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { in vc4_crtc_mode_valid()
667 crtc->base.id); in vc4_crtc_mode_valid()
683 *left = vc4_state->margins.left; in vc4_crtc_get_margins()
684 *right = vc4_state->margins.right; in vc4_crtc_get_margins()
685 *top = vc4_state->margins.top; in vc4_crtc_get_margins()
686 *bottom = vc4_state->margins.bottom; in vc4_crtc_get_margins()
693 for_each_new_connector_in_state(state->state, conn, conn_state, i) { in vc4_crtc_get_margins()
694 if (conn_state->crtc != state->crtc) in vc4_crtc_get_margins()
697 *left = conn_state->tv.margins.left; in vc4_crtc_get_margins()
698 *right = conn_state->tv.margins.right; in vc4_crtc_get_margins()
699 *top = conn_state->tv.margins.top; in vc4_crtc_get_margins()
700 *bottom = conn_state->tv.margins.bottom; in vc4_crtc_get_margins()
722 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; in vc4_crtc_atomic_check()
725 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) { in vc4_crtc_atomic_check()
726 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000, in vc4_crtc_atomic_check()
727 mode->clock * 9 / 10) * 1000; in vc4_crtc_atomic_check()
729 vc4_state->hvs_load = mode->clock * 1000; in vc4_crtc_atomic_check()
735 if (conn_state->crtc != crtc) in vc4_crtc_atomic_check()
738 vc4_state->margins.left = conn_state->tv.margins.left; in vc4_crtc_atomic_check()
739 vc4_state->margins.right = conn_state->tv.margins.right; in vc4_crtc_atomic_check()
740 vc4_state->margins.top = conn_state->tv.margins.top; in vc4_crtc_atomic_check()
741 vc4_state->margins.bottom = conn_state->tv.margins.bottom; in vc4_crtc_atomic_check()
751 struct drm_device *dev = crtc->dev; in vc4_enable_vblank()
755 return -ENODEV; in vc4_enable_vblank()
767 struct drm_device *dev = crtc->dev; in vc4_disable_vblank()
780 struct drm_crtc *crtc = &vc4_crtc->base; in vc4_crtc_handle_page_flip()
781 struct drm_device *dev = crtc->dev; in vc4_crtc_handle_page_flip()
783 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_handle_page_flip()
784 u32 chan = vc4_crtc->current_hvs_channel; in vc4_crtc_handle_page_flip()
787 spin_lock_irqsave(&dev->event_lock, flags); in vc4_crtc_handle_page_flip()
788 spin_lock(&vc4_crtc->irq_lock); in vc4_crtc_handle_page_flip()
789 if (vc4_crtc->event && in vc4_crtc_handle_page_flip()
790 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || in vc4_crtc_handle_page_flip()
791 vc4_crtc->feeds_txp)) { in vc4_crtc_handle_page_flip()
792 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); in vc4_crtc_handle_page_flip()
793 vc4_crtc->event = NULL; in vc4_crtc_handle_page_flip()
804 spin_unlock(&vc4_crtc->irq_lock); in vc4_crtc_handle_page_flip()
805 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_crtc_handle_page_flip()
810 crtc->t_vblank = ktime_get(); in vc4_crtc_handle_vblank()
811 drm_crtc_handle_vblank(&crtc->base); in vc4_crtc_handle_vblank()
848 struct drm_crtc *crtc = flip_state->crtc; in vc4_async_page_flip_complete()
849 struct drm_device *dev = crtc->dev; in vc4_async_page_flip_complete()
850 struct drm_plane *plane = crtc->primary; in vc4_async_page_flip_complete()
852 vc4_plane_async_set_fb(plane, flip_state->fb); in vc4_async_page_flip_complete()
853 if (flip_state->event) { in vc4_async_page_flip_complete()
856 spin_lock_irqsave(&dev->event_lock, flags); in vc4_async_page_flip_complete()
857 drm_crtc_send_vblank_event(crtc, flip_state->event); in vc4_async_page_flip_complete()
858 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_async_page_flip_complete()
862 drm_framebuffer_put(flip_state->fb); in vc4_async_page_flip_complete()
864 if (flip_state->old_fb) in vc4_async_page_flip_complete()
865 drm_framebuffer_put(flip_state->old_fb); in vc4_async_page_flip_complete()
876 if (flip_state->old_fb) { in vc4_async_page_flip_seqno_complete()
878 drm_fb_dma_get_gem_obj(flip_state->old_fb, 0); in vc4_async_page_flip_seqno_complete()
879 bo = to_vc4_bo(&dma_bo->base); in vc4_async_page_flip_seqno_complete()
889 * FIXME: we should move to generic async-page-flip when in vc4_async_page_flip_seqno_complete()
891 * hand-made cleanup_fb() logic. in vc4_async_page_flip_seqno_complete()
910 struct drm_framebuffer *fb = flip_state->fb; in vc4_async_set_fence_cb()
916 if (!vc4->is_vc5) { in vc4_async_set_fence_cb()
917 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); in vc4_async_set_fence_cb()
919 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno, in vc4_async_set_fence_cb()
923 ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence); in vc4_async_set_fence_cb()
929 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence); in vc4_async_set_fence_cb()
934 if (dma_fence_add_callback(fence, &flip_state->cb.fence, in vc4_async_set_fence_cb()
936 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence); in vc4_async_set_fence_cb()
947 struct drm_device *dev = crtc->dev; in vc4_async_page_flip_common()
948 struct drm_plane *plane = crtc->primary; in vc4_async_page_flip_common()
953 return -ENOMEM; in vc4_async_page_flip_common()
956 flip_state->fb = fb; in vc4_async_page_flip_common()
957 flip_state->crtc = crtc; in vc4_async_page_flip_common()
958 flip_state->event = event; in vc4_async_page_flip_common()
964 * FIXME: we should move to generic async-page-flip when it's in vc4_async_page_flip_common()
965 * available, so that we can get rid of this hand-made cleanup_fb() in vc4_async_page_flip_common()
968 flip_state->old_fb = plane->state->fb; in vc4_async_page_flip_common()
969 if (flip_state->old_fb) in vc4_async_page_flip_common()
970 drm_framebuffer_get(flip_state->old_fb); in vc4_async_page_flip_common()
978 drm_atomic_set_fb_for_plane(plane->state, fb); in vc4_async_page_flip_common()
986 /* Implements async (non-vblank-synced) page flips.
997 struct drm_device *dev = crtc->dev; in vc4_async_page_flip()
1000 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); in vc4_async_page_flip()
1003 if (WARN_ON_ONCE(vc4->is_vc5)) in vc4_async_page_flip()
1004 return -ENODEV; in vc4_async_page_flip()
1009 * plane is later updated through the non-async path. in vc4_async_page_flip()
1011 * FIXME: we should move to generic async-page-flip when in vc4_async_page_flip()
1013 * hand-made prepare_fb() logic. in vc4_async_page_flip()
1043 struct drm_device *dev = crtc->dev; in vc4_page_flip()
1046 if (vc4->is_vc5) in vc4_page_flip()
1063 old_vc4_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_duplicate_state()
1064 vc4_state->margins = old_vc4_state->margins; in vc4_crtc_duplicate_state()
1065 vc4_state->assigned_channel = old_vc4_state->assigned_channel; in vc4_crtc_duplicate_state()
1067 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); in vc4_crtc_duplicate_state()
1068 return &vc4_state->base; in vc4_crtc_duplicate_state()
1074 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); in vc4_crtc_destroy_state()
1077 if (drm_mm_node_allocated(&vc4_state->mm)) { in vc4_crtc_destroy_state()
1080 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); in vc4_crtc_destroy_state()
1081 drm_mm_remove_node(&vc4_state->mm); in vc4_crtc_destroy_state()
1082 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); in vc4_crtc_destroy_state()
1093 if (crtc->state) in vc4_crtc_reset()
1094 vc4_crtc_destroy_state(crtc, crtc->state); in vc4_crtc_reset()
1098 crtc->state = NULL; in vc4_crtc_reset()
1102 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_crtc_reset()
1103 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); in vc4_crtc_reset()
1108 struct drm_device *drm = crtc->dev; in vc4_crtc_late_register()
1112 vc4_debugfs_add_regset32(drm, crtc_data->debugfs_name, in vc4_crtc_late_register()
1113 &vc4_crtc->regset); in vc4_crtc_late_register()
1145 .name = "pixelvalve-0",
1160 .name = "pixelvalve-1",
1175 .name = "pixelvalve-2",
1190 .name = "pixelvalve-0",
1205 .name = "pixelvalve-1",
1220 .name = "pixelvalve-2",
1234 .name = "pixelvalve-3",
1248 .name = "pixelvalve-4",
1261 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1262 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1263 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1264 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1265 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1266 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1267 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1268 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1277 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; in vc4_set_crtc_possible_masks()
1284 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) in vc4_set_crtc_possible_masks()
1288 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { in vc4_set_crtc_possible_masks()
1289 if (vc4_encoder->type == encoder_types[i]) { in vc4_set_crtc_possible_masks()
1290 vc4_encoder->clock_select = i; in vc4_set_crtc_possible_masks()
1291 encoder->possible_crtcs |= drm_crtc_mask(crtc); in vc4_set_crtc_possible_masks()
1299 * __vc4_crtc_init - Initializes a CRTC
1326 struct drm_crtc *crtc = &vc4_crtc->base; in __vc4_crtc_init()
1330 vc4_crtc->data = data; in __vc4_crtc_init()
1331 vc4_crtc->pdev = pdev; in __vc4_crtc_init()
1332 vc4_crtc->feeds_txp = feeds_txp; in __vc4_crtc_init()
1333 spin_lock_init(&vc4_crtc->irq_lock); in __vc4_crtc_init()
1335 crtc_funcs, data->name); in __vc4_crtc_init()
1341 if (!vc4->is_vc5) { in __vc4_crtc_init()
1342 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); in __vc4_crtc_init()
1344 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); in __vc4_crtc_init()
1349 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); in __vc4_crtc_init()
1352 for (i = 0; i < crtc->gamma_size; i++) { in __vc4_crtc_init()
1353 vc4_crtc->lut_r[i] = i; in __vc4_crtc_init()
1354 vc4_crtc->lut_g[i] = i; in __vc4_crtc_init()
1355 vc4_crtc->lut_b[i] = i; in __vc4_crtc_init()
1378 dev_err(drm->dev, "failed to construct primary plane\n"); in vc4_crtc_init()
1397 return -ENOMEM; in vc4_crtc_bind()
1398 crtc = &vc4_crtc->base; in vc4_crtc_bind()
1402 return -ENODEV; in vc4_crtc_bind()
1404 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); in vc4_crtc_bind()
1405 if (IS_ERR(vc4_crtc->regs)) in vc4_crtc_bind()
1406 return PTR_ERR(vc4_crtc->regs); in vc4_crtc_bind()
1408 vc4_crtc->regset.base = vc4_crtc->regs; in vc4_crtc_bind()
1409 vc4_crtc->regset.regs = crtc_regs; in vc4_crtc_bind()
1410 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); in vc4_crtc_bind()
1412 ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base, in vc4_crtc_bind()
1451 return component_add(&pdev->dev, &vc4_crtc_ops); in vc4_crtc_dev_probe()
1456 component_del(&pdev->dev, &vc4_crtc_ops); in vc4_crtc_dev_remove()