121 static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val)  in wreg_crt()  function
184 	wreg_crt(cirrus, 0x0c, (u8)((addr >> 8) & 0xff));  in cirrus_set_start_address()
185 	wreg_crt(cirrus, 0x0d, (u8)(addr & 0xff));  in cirrus_set_start_address()
191 	wreg_crt(cirrus, 0x1b, tmp);  in cirrus_set_start_address()
196 	wreg_crt(cirrus, 0x1d, tmp);  in cirrus_set_start_address()
222 	wreg_crt(cirrus, VGA_CRTC_V_SYNC_END, 0x20);  in cirrus_mode_set()
223 	wreg_crt(cirrus, VGA_CRTC_H_TOTAL, htotal);  in cirrus_mode_set()
224 	wreg_crt(cirrus, VGA_CRTC_H_DISP, hdispend);  in cirrus_mode_set()
225 	wreg_crt(cirrus, VGA_CRTC_H_SYNC_START, hsyncstart);  in cirrus_mode_set()
226 	wreg_crt(cirrus, VGA_CRTC_H_SYNC_END, hsyncend);  in cirrus_mode_set()
227 	wreg_crt(cirrus, VGA_CRTC_V_TOTAL, vtotal & 0xff);  in cirrus_mode_set()
228 	wreg_crt(cirrus, VGA_CRTC_V_DISP_END, vdispend & 0xff);  in cirrus_mode_set()
233 	wreg_crt(cirrus, VGA_CRTC_MAX_SCAN, tmp);  in cirrus_mode_set()
249 	wreg_crt(cirrus, VGA_CRTC_OVERFLOW, tmp);  in cirrus_mode_set()
264 	wreg_crt(cirrus, CL_CRT1A, tmp);  in cirrus_mode_set()
267 	wreg_crt(cirrus, VGA_CRTC_MODE, 0x03);  in cirrus_mode_set()
316 	wreg_crt(cirrus, VGA_CRTC_OFFSET, cr13);  in cirrus_pitch_set()
322 	wreg_crt(cirrus, 0x1b, cr1b);  in cirrus_pitch_set()