371 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)  in dispc_vid_write()  argument
373 	void __iomem *base = dispc->base_vid[hw_plane];  in dispc_vid_write()
378 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)  in dispc_vid_read()  argument
380 	void __iomem *base = dispc->base_vid[hw_plane];  in dispc_vid_read()
452 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,  in VID_REG_GET()  argument
455 	return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);  in VID_REG_GET()
458 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,  in VID_REG_FLD_MOD()  argument
461 	dispc_vid_write(dispc, hw_plane, idx,  in VID_REG_FLD_MOD()
462 			FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),  in VID_REG_FLD_MOD()
526 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane)  in dispc_vid_irq_from_raw()  argument
531 		vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane);  in dispc_vid_irq_from_raw()
536 static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane)  in dispc_vid_irq_to_raw()  argument
540 	if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane))  in dispc_vid_irq_to_raw()
563 						u32 hw_plane)  in dispc_k2g_vid_read_irqstatus()  argument
565 	u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);  in dispc_k2g_vid_read_irqstatus()
567 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k2g_vid_read_irqstatus()
571 					  u32 hw_plane, dispc_irq_t vidstat)  in dispc_k2g_vid_write_irqstatus()  argument
573 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k2g_vid_write_irqstatus()
575 	dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);  in dispc_k2g_vid_write_irqstatus()
595 						u32 hw_plane)  in dispc_k2g_vid_read_irqenable()  argument
597 	u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);  in dispc_k2g_vid_read_irqenable()
599 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k2g_vid_read_irqenable()
603 					u32 hw_plane, dispc_irq_t vidstat)  in dispc_k2g_vid_set_irqenable()  argument
605 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k2g_vid_set_irqenable()
607 	dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);  in dispc_k2g_vid_set_irqenable()
681 					       u32 hw_plane)  in dispc_k3_vid_read_irqstatus()  argument
683 	u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));  in dispc_k3_vid_read_irqstatus()
685 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k3_vid_read_irqstatus()
689 					 u32 hw_plane, dispc_irq_t vidstat)  in dispc_k3_vid_write_irqstatus()  argument
691 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k3_vid_write_irqstatus()
693 	dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);  in dispc_k3_vid_write_irqstatus()
713 					       u32 hw_plane)  in dispc_k3_vid_read_irqenable()  argument
715 	u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));  in dispc_k3_vid_read_irqenable()
717 	return dispc_vid_irq_from_raw(stat, hw_plane);  in dispc_k3_vid_read_irqenable()
721 				       u32 hw_plane, dispc_irq_t vidstat)  in dispc_k3_vid_set_irqenable()  argument
723 	u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);  in dispc_k3_vid_set_irqenable()
725 	dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);  in dispc_k3_vid_set_irqenable()
1295 				    u32 hw_plane, u32 hw_videoport,  in dispc_k2g_ovr_set_plane()  argument
1299 	dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,  in dispc_k2g_ovr_set_plane()
1304 				      u32 hw_plane, u32 hw_videoport,  in dispc_am65x_ovr_set_plane()  argument
1308 			hw_plane, 4, 1);  in dispc_am65x_ovr_set_plane()
1316 				      u32 hw_plane, u32 hw_videoport,  in dispc_j721e_ovr_set_plane()  argument
1320 			hw_plane, 4, 1);  in dispc_j721e_ovr_set_plane()
1327 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,  in dispc_ovr_set_plane()  argument
1332 		dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,  in dispc_ovr_set_plane()
1337 		dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,  in dispc_ovr_set_plane()
1341 		dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,  in dispc_ovr_set_plane()
1439 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,  in dispc_k2g_vid_write_csc()  argument
1458 		dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],  in dispc_k2g_vid_write_csc()
1462 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,  in dispc_k3_vid_write_csc()  argument
1477 		dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],  in dispc_k3_vid_write_csc()
1559 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,  in dispc_vid_csc_setup()  argument
1572 		dispc_k2g_vid_write_csc(dispc, hw_plane, coef);  in dispc_vid_csc_setup()
1574 		dispc_k3_vid_write_csc(dispc, hw_plane, coef);  in dispc_vid_csc_setup()
1577 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,  in dispc_vid_csc_enable()  argument
1580 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);  in dispc_vid_csc_enable()
1598 				      u32 hw_plane,  in dispc_vid_write_fir_coefs()  argument
1629 		dispc_vid_write(dispc, hw_plane, reg, c0);  in dispc_vid_write_fir_coefs()
1641 		dispc_vid_write(dispc, hw_plane, reg, c12);  in dispc_vid_write_fir_coefs()
1831 				  u32 hw_plane,  in dispc_vid_set_scaling()  argument
1836 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_vid_set_scaling()
1840 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_vid_set_scaling()
1848 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_vid_set_scaling()
1853 			dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,  in dispc_vid_set_scaling()
1855 			dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1860 			dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,  in dispc_vid_set_scaling()
1862 			dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1869 		dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);  in dispc_vid_set_scaling()
1870 		dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1876 		dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);  in dispc_vid_set_scaling()
1877 		dispc_vid_write_fir_coefs(dispc, hw_plane,  in dispc_vid_set_scaling()
1931 					 u32 hw_plane, u32 fourcc)  in dispc_plane_set_pixel_format()  argument
1937 			VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,  in dispc_plane_set_pixel_format()
1969 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,  in dispc_plane_check()  argument
1973 	bool lite = dispc->feat->vid_lite[hw_plane];  in dispc_plane_check()
1986 				state->color_range, hw_plane);  in dispc_plane_check()
1995 				__func__, hw_plane,  in dispc_plane_check()
2040 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,  in dispc_plane_setup()  argument
2044 	bool lite = dispc->feat->vid_lite[hw_plane];  in dispc_plane_setup()
2053 	dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);  in dispc_plane_setup()
2055 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);  in dispc_plane_setup()
2056 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);  in dispc_plane_setup()
2057 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);  in dispc_plane_setup()
2058 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);  in dispc_plane_setup()
2060 	dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,  in dispc_plane_setup()
2065 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,  in dispc_plane_setup()
2068 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,  in dispc_plane_setup()
2071 	dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,  in dispc_plane_setup()
2081 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2083 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2085 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2087 		dispc_vid_write(dispc, hw_plane,  in dispc_plane_setup()
2090 		dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,  in dispc_plane_setup()
2097 		dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,  in dispc_plane_setup()
2101 		dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);  in dispc_plane_setup()
2106 		dispc_vid_csc_setup(dispc, hw_plane, state);  in dispc_plane_setup()
2107 		dispc_vid_csc_enable(dispc, hw_plane, true);  in dispc_plane_setup()
2109 		dispc_vid_csc_enable(dispc, hw_plane, false);  in dispc_plane_setup()
2112 	dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,  in dispc_plane_setup()
2116 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,  in dispc_plane_setup()
2119 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,  in dispc_plane_setup()
2123 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)  in dispc_plane_enable()  argument
2125 	VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);  in dispc_plane_enable()
2128 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)  in dispc_vid_get_fifo_size()  argument
2130 	return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);  in dispc_vid_get_fifo_size()
2134 					  u32 hw_plane, u32 low, u32 high)  in dispc_vid_set_mflag_threshold()  argument
2136 	dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,  in dispc_vid_set_mflag_threshold()
2141 					u32 hw_plane, u32 low, u32 high)  in dispc_vid_set_buf_threshold()  argument
2143 	dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,  in dispc_vid_set_buf_threshold()
2149 	unsigned int hw_plane;  in dispc_k2g_plane_init()  local
2158 	for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {  in dispc_k2g_plane_init()
2159 		u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);  in dispc_k2g_plane_init()
2174 			dispc->feat->vid_name[hw_plane],  in dispc_k2g_plane_init()
2180 		dispc_vid_set_buf_threshold(dispc, hw_plane,  in dispc_k2g_plane_init()
2182 		dispc_vid_set_mflag_threshold(dispc, hw_plane,  in dispc_k2g_plane_init()
2185 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);  in dispc_k2g_plane_init()
2192 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,  in dispc_k2g_plane_init()
2199 	unsigned int hw_plane;  in dispc_k3_plane_init()  local
2213 	for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {  in dispc_k3_plane_init()
2214 		u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);  in dispc_k3_plane_init()
2229 			dispc->feat->vid_name[hw_plane],  in dispc_k3_plane_init()
2235 		dispc_vid_set_buf_threshold(dispc, hw_plane,  in dispc_k3_plane_init()
2237 		dispc_vid_set_mflag_threshold(dispc, hw_plane,  in dispc_k3_plane_init()
2240 		dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);  in dispc_k3_plane_init()
2243 		VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,  in dispc_k3_plane_init()