Lines Matching +full:j721e +full:- +full:dss
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/dma-mapping.h>
14 #include <linux/media-bus-format.h>
79 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
82 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
155 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
158 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
244 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
247 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
292 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
295 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
362 iowrite32(val, dispc->base_common + reg); in dispc_write()
367 return ioread32(dispc->base_common + reg); in dispc_read()
373 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
380 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
388 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
395 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
403 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
410 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
422 return ((1 << (start - end + 1)) - 1) << end; in FLD_MASK()
733 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
737 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
741 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
757 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
760 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
773 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
776 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
794 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
802 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
825 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
840 switch (dispc->feat->subrev) { in dispc_set_irqenable()
897 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
898 tstate->bus_flags); in dispc_vp_bus_check()
900 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
901 __func__, tstate->bus_format); in dispc_vp_bus_check()
902 return -EINVAL; in dispc_vp_bus_check()
905 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
906 fmt->is_oldi_fmt) { in dispc_vp_bus_check()
907 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
908 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
909 return -EINVAL; in dispc_vp_bus_check()
919 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
922 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
924 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
926 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
928 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
930 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
972 if (fmt->data_width == 24) in dispc_enable_oldi()
974 else if (fmt->data_width != 18) in dispc_enable_oldi()
975 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
976 __func__, fmt->data_width); in dispc_enable_oldi()
980 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); in dispc_enable_oldi()
993 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
1003 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
1004 tstate->bus_flags); in dispc_vp_prepare()
1009 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
1019 const struct drm_display_mode *mode = &state->adjusted_mode; in dispc_vp_enable()
1025 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
1026 tstate->bus_flags); in dispc_vp_enable()
1031 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
1033 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_enable()
1034 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_enable()
1035 hbp = mode->htotal - mode->hsync_end; in dispc_vp_enable()
1037 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_enable()
1038 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_enable()
1039 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_enable()
1042 FLD_VAL(hsw - 1, 7, 0) | in dispc_vp_enable()
1043 FLD_VAL(hfp - 1, 19, 8) | in dispc_vp_enable()
1044 FLD_VAL(hbp - 1, 31, 20)); in dispc_vp_enable()
1047 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
1051 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); in dispc_vp_enable()
1053 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); in dispc_vp_enable()
1055 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); in dispc_vp_enable()
1057 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); in dispc_vp_enable()
1062 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); in dispc_vp_enable()
1068 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1081 FLD_VAL(mode->hdisplay - 1, 11, 0) | in dispc_vp_enable()
1082 FLD_VAL(mode->vdisplay - 1, 27, 16)); in dispc_vp_enable()
1094 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1173 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1175 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1180 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1183 if (mode->clock > max_pclk) in dispc_vp_mode_valid()
1186 if (mode->hdisplay > 4096) in dispc_vp_mode_valid()
1189 if (mode->vdisplay > 4096) in dispc_vp_mode_valid()
1193 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dispc_vp_mode_valid()
1199 * - YUV output selected (BT656, BT1120) in dispc_vp_mode_valid()
1200 * - Dithering enabled in dispc_vp_mode_valid()
1201 * - TDM with TDMCycleFormat == 3 in dispc_vp_mode_valid()
1204 if ((mode->hdisplay % 2) != 0) in dispc_vp_mode_valid()
1207 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_mode_valid()
1208 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_mode_valid()
1209 hbp = mode->htotal - mode->hsync_end; in dispc_vp_mode_valid()
1211 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_mode_valid()
1212 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_mode_valid()
1213 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_mode_valid()
1224 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1228 bandwidth = 1000 * mode->clock; in dispc_vp_mode_valid()
1229 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; in dispc_vp_mode_valid()
1230 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); in dispc_vp_mode_valid()
1232 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1241 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1244 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1252 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1264 return (unsigned int)(abs(((rr - r) * 100) / r)); in dispc_pclk_diff()
1273 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1275 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1280 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1283 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1287 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1288 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1330 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1353 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1394 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1395 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1396 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1404 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1405 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1406 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
1407 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); in dispc_csc_yuv2rgb_regval()
1408 regval[4] = CVAL(csc->m[CSC_BCB], 0); in dispc_csc_yuv2rgb_regval()
1416 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); in dispc_csc_rgb2yuv_regval()
1417 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); in dispc_csc_rgb2yuv_regval()
1418 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); in dispc_csc_rgb2yuv_regval()
1419 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); in dispc_csc_rgb2yuv_regval()
1420 regval[4] = CVAL(csc->m[CSC_CBB], 0); in dispc_csc_rgb2yuv_regval()
1428 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); in dispc_csc_cpr_regval()
1429 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); in dispc_csc_cpr_regval()
1430 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); in dispc_csc_cpr_regval()
1431 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); in dispc_csc_cpr_regval()
1432 regval[4] = CVAL(csc->m[CSC_BB], 0); in dispc_csc_cpr_regval()
1451 csc->to_regval(csc, regval); in dispc_k2g_vid_write_csc()
1454 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1455 __func__, csc->name); in dispc_k2g_vid_write_csc()
1474 csc->to_regval(csc, regval); in dispc_k3_vid_write_csc()
1481 /* YUV -> RGB, ITU-R BT.601, full range */
1485 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1487 { 0, -2048, -2048, }, /* full range */
1493 /* YUV -> RGB, ITU-R BT.601, limited range */
1497 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1499 { -256, -2048, -2048, }, /* limited range */
1505 /* YUV -> RGB, ITU-R BT.709, full range */
1509 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1511 { 0, -2048, -2048, }, /* full range */
1517 /* YUV -> RGB, ITU-R BT.709, limited range */
1521 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1523 { -256, -2048, -2048, }, /* limited range */
1564 coef = dispc_find_csc(state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1566 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1567 __func__, state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1571 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1621 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1627 u16 c0 = coefs->c0[phase]; in dispc_vid_write_fir_coefs()
1637 c1 = coefs->c1[phase]; in dispc_vid_write_fir_coefs()
1638 c2 = coefs->c2[phase]; in dispc_vid_write_fir_coefs()
1671 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1672 u32 fourcc = state->fb->format->format; in dispc_vid_calc_scaling()
1673 u32 in_width_max_5tap = f->in_width_max_5tap_rgb; in dispc_vid_calc_scaling()
1674 u32 in_width_max_3tap = f->in_width_max_3tap_rgb; in dispc_vid_calc_scaling()
1679 sp->xinc = 1; in dispc_vid_calc_scaling()
1680 sp->yinc = 1; in dispc_vid_calc_scaling()
1681 sp->in_w = state->src_w >> 16; in dispc_vid_calc_scaling()
1682 sp->in_w_uv = sp->in_w; in dispc_vid_calc_scaling()
1683 sp->in_h = state->src_h >> 16; in dispc_vid_calc_scaling()
1684 sp->in_h_uv = sp->in_h; in dispc_vid_calc_scaling()
1686 sp->scale_x = sp->in_w != state->crtc_w; in dispc_vid_calc_scaling()
1687 sp->scale_y = sp->in_h != state->crtc_h; in dispc_vid_calc_scaling()
1690 in_width_max_5tap = f->in_width_max_5tap_yuv; in dispc_vid_calc_scaling()
1691 in_width_max_3tap = f->in_width_max_3tap_yuv; in dispc_vid_calc_scaling()
1693 sp->in_w_uv >>= 1; in dispc_vid_calc_scaling()
1694 sp->scale_x = true; in dispc_vid_calc_scaling()
1697 sp->in_h_uv >>= 1; in dispc_vid_calc_scaling()
1698 sp->scale_y = true; in dispc_vid_calc_scaling()
1703 if ((!sp->scale_x && !sp->scale_y) || lite_plane) in dispc_vid_calc_scaling()
1706 if (sp->in_w > in_width_max_5tap) { in dispc_vid_calc_scaling()
1707 sp->five_taps = false; in dispc_vid_calc_scaling()
1709 downscale_limit = f->downscale_limit_3tap; in dispc_vid_calc_scaling()
1711 sp->five_taps = true; in dispc_vid_calc_scaling()
1713 downscale_limit = f->downscale_limit_5tap; in dispc_vid_calc_scaling()
1716 if (sp->scale_x) { in dispc_vid_calc_scaling()
1717 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1719 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1720 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1721 "%s: X-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1722 __func__, state->crtc_w, state->src_w >> 16, in dispc_vid_calc_scaling()
1723 f->upscale_limit); in dispc_vid_calc_scaling()
1724 return -EINVAL; in dispc_vid_calc_scaling()
1727 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1728 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, in dispc_vid_calc_scaling()
1729 state->crtc_w), in dispc_vid_calc_scaling()
1732 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1733 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1734 "%s: X-scaling factor %u/%u < 1/%u\n", in dispc_vid_calc_scaling()
1735 __func__, state->crtc_w, in dispc_vid_calc_scaling()
1736 state->src_w >> 16, in dispc_vid_calc_scaling()
1737 downscale_limit * f->xinc_max); in dispc_vid_calc_scaling()
1738 return -EINVAL; in dispc_vid_calc_scaling()
1741 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1744 while (sp->in_w > in_width_max) { in dispc_vid_calc_scaling()
1745 sp->xinc++; in dispc_vid_calc_scaling()
1746 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1749 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1750 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1752 state->src_w >> 16, in_width_max * f->xinc_max); in dispc_vid_calc_scaling()
1753 return -EINVAL; in dispc_vid_calc_scaling()
1762 sp->in_w &= ~1; in dispc_vid_calc_scaling()
1764 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1767 if (sp->scale_y) { in dispc_vid_calc_scaling()
1768 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); in dispc_vid_calc_scaling()
1770 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1771 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1772 "%s: Y-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1773 __func__, state->crtc_h, state->src_h >> 16, in dispc_vid_calc_scaling()
1774 f->upscale_limit); in dispc_vid_calc_scaling()
1775 return -EINVAL; in dispc_vid_calc_scaling()
1778 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1779 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, in dispc_vid_calc_scaling()
1780 state->crtc_h), in dispc_vid_calc_scaling()
1783 sp->in_h /= sp->yinc; in dispc_vid_calc_scaling()
1784 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, in dispc_vid_calc_scaling()
1785 state->crtc_h); in dispc_vid_calc_scaling()
1789 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1790 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", in dispc_vid_calc_scaling()
1791 __func__, state->src_w >> 16, state->src_h >> 16, in dispc_vid_calc_scaling()
1792 sp->xinc, sp->yinc, sp->in_w, sp->in_h, in dispc_vid_calc_scaling()
1793 sp->fir_xinc / 0x200000u, in dispc_vid_calc_scaling()
1794 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1795 sp->fir_yinc / 0x200000u, in dispc_vid_calc_scaling()
1796 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1797 sp->five_taps ? 5 : 3, in dispc_vid_calc_scaling()
1798 state->crtc_w, state->crtc_h); in dispc_vid_calc_scaling()
1801 if (sp->scale_x) { in dispc_vid_calc_scaling()
1802 sp->in_w_uv /= sp->xinc; in dispc_vid_calc_scaling()
1803 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, in dispc_vid_calc_scaling()
1804 state->crtc_w); in dispc_vid_calc_scaling()
1805 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1806 sp->fir_xinc_uv, in dispc_vid_calc_scaling()
1809 if (sp->scale_y) { in dispc_vid_calc_scaling()
1810 sp->in_h_uv /= sp->yinc; in dispc_vid_calc_scaling()
1811 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, in dispc_vid_calc_scaling()
1812 state->crtc_h); in dispc_vid_calc_scaling()
1813 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1814 sp->fir_yinc_uv, in dispc_vid_calc_scaling()
1815 sp->five_taps); in dispc_vid_calc_scaling()
1819 if (sp->scale_x) in dispc_vid_calc_scaling()
1820 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1823 if (sp->scale_y) in dispc_vid_calc_scaling()
1824 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1825 sp->five_taps); in dispc_vid_calc_scaling()
1837 sp->scale_x, 7, 7); in dispc_vid_set_scaling()
1841 sp->scale_y, 8, 8); in dispc_vid_set_scaling()
1844 if (!sp->scale_x && !sp->scale_y) in dispc_vid_set_scaling()
1847 /* VERTICAL 5-TAPS */ in dispc_vid_set_scaling()
1849 sp->five_taps, 21, 21); in dispc_vid_set_scaling()
1852 if (sp->scale_x) { in dispc_vid_set_scaling()
1854 sp->fir_xinc_uv); in dispc_vid_set_scaling()
1857 sp->xcoef_uv); in dispc_vid_set_scaling()
1859 if (sp->scale_y) { in dispc_vid_set_scaling()
1861 sp->fir_yinc_uv); in dispc_vid_set_scaling()
1864 sp->ycoef_uv); in dispc_vid_set_scaling()
1868 if (sp->scale_x) { in dispc_vid_set_scaling()
1869 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1872 sp->xcoef); in dispc_vid_set_scaling()
1875 if (sp->scale_y) { in dispc_vid_set_scaling()
1876 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1878 DISPC_VID_FIR_COEF_VERT, sp->ycoef); in dispc_vid_set_scaling()
1949 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
1951 *len = dispc->num_fourccs; in dispc_plane_formats()
1953 return dispc->fourccs; in dispc_plane_formats()
1961 return 1 + (pixels - 1) * ps; in pixinc()
1963 return 1 - (-pixels + 1) * ps; in pixinc()
1973 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1974 u32 fourcc = state->fb->format->format; in dispc_plane_check()
1975 bool need_scaling = state->src_w >> 16 != state->crtc_w || in dispc_plane_check()
1976 state->src_h >> 16 != state->crtc_h; in dispc_plane_check()
1981 if (!dispc_find_csc(state->color_encoding, in dispc_plane_check()
1982 state->color_range)) { in dispc_plane_check()
1983 dev_dbg(dispc->dev, in dispc_plane_check()
1985 __func__, state->color_encoding, in dispc_plane_check()
1986 state->color_range, hw_plane); in dispc_plane_check()
1987 return -EINVAL; in dispc_plane_check()
1993 dev_dbg(dispc->dev, in dispc_plane_check()
1996 state->src_w >> 16, state->src_h >> 16, in dispc_plane_check()
1997 state->crtc_w, state->crtc_h); in dispc_plane_check()
1998 return -EINVAL; in dispc_plane_check()
2011 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_dma_addr()
2013 u32 x = state->src_x >> 16; in dispc_plane_state_dma_addr()
2014 u32 y = state->src_y >> 16; in dispc_plane_state_dma_addr()
2016 gem = drm_fb_dma_get_gem_obj(state->fb, 0); in dispc_plane_state_dma_addr()
2018 return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] + in dispc_plane_state_dma_addr()
2019 y * fb->pitches[0]; in dispc_plane_state_dma_addr()
2025 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_p_uv_addr()
2027 u32 x = state->src_x >> 16; in dispc_plane_state_p_uv_addr()
2028 u32 y = state->src_y >> 16; in dispc_plane_state_p_uv_addr()
2030 if (WARN_ON(state->fb->format->num_planes != 2)) in dispc_plane_state_p_uv_addr()
2035 return gem->dma_addr + fb->offsets[1] + in dispc_plane_state_p_uv_addr()
2036 (x * fb->format->cpp[1] / fb->format->hsub) + in dispc_plane_state_p_uv_addr()
2037 (y * fb->pitches[1] / fb->format->vsub); in dispc_plane_state_p_uv_addr()
2044 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
2045 u32 fourcc = state->fb->format->format; in dispc_plane_setup()
2046 u16 cpp = state->fb->format->cpp[0]; in dispc_plane_setup()
2047 u32 fb_width = state->fb->pitches[0] / cpp; in dispc_plane_setup()
2061 (scale.in_w - 1) | ((scale.in_h - 1) << 16)); in dispc_plane_setup()
2072 pixinc(1 + (scale.yinc * fb_width - in dispc_plane_setup()
2076 if (state->fb->format->num_planes == 2) { in dispc_plane_setup()
2077 u16 cpp_uv = state->fb->format->cpp[1]; in dispc_plane_setup()
2078 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; in dispc_plane_setup()
2091 pixinc(1 + (scale.yinc * fb_width_uv - in dispc_plane_setup()
2098 (state->crtc_w - 1) | in dispc_plane_setup()
2099 ((state->crtc_h - 1) << 16)); in dispc_plane_setup()
2104 /* enable YUV->RGB color conversion */ in dispc_plane_setup()
2113 0xFF & (state->alpha >> 8)); in dispc_plane_setup()
2115 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) in dispc_plane_setup()
2151 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2158 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2164 thr_high = size - 1; in dispc_k2g_plane_init()
2172 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2174 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2188 * Prefetch up to fifo high-threshold value to minimize the in dispc_k2g_plane_init()
2203 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2213 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2219 thr_high = size - 1; in dispc_k3_plane_init()
2227 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2229 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2250 switch (dispc->feat->subrev) { in dispc_plane_init()
2268 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2270 /* Enable the gamma Shadow bit-field for all VPs*/ in dispc_vp_init()
2271 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2280 /* Note: Hardcoded DPI routing on J721E for now */ in dispc_initial_config()
2281 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2292 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2293 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2296 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2298 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2314 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2315 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2318 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2320 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2335 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2336 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2339 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2341 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2357 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2384 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2385 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2389 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2392 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2402 for (i = 0; i < length - 1; ++i) { in dispc_vp_set_gamma()
2403 unsigned int first = i * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2404 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2405 unsigned int w = last - first; in dispc_vp_set_gamma()
2413 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; in dispc_vp_set_gamma()
2414 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; in dispc_vp_set_gamma()
2415 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; in dispc_vp_set_gamma()
2417 r >>= 16 - hwbits; in dispc_vp_set_gamma()
2418 g >>= 16 - hwbits; in dispc_vp_set_gamma()
2419 b >>= 16 - hwbits; in dispc_vp_set_gamma()
2436 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); in dispc_S31_32_to_s2_8()
2448 cpr->to_regval = dispc_csc_cpr_regval; in dispc_k2g_cpr_from_ctm()
2449 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); in dispc_k2g_cpr_from_ctm()
2450 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); in dispc_k2g_cpr_from_ctm()
2451 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); in dispc_k2g_cpr_from_ctm()
2452 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); in dispc_k2g_cpr_from_ctm()
2453 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); in dispc_k2g_cpr_from_ctm()
2454 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); in dispc_k2g_cpr_from_ctm()
2455 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); in dispc_k2g_cpr_from_ctm()
2456 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); in dispc_k2g_cpr_from_ctm()
2457 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); in dispc_k2g_cpr_from_ctm()
2466 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); in dispc_k2g_vp_csc_cpr_regval()
2467 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); in dispc_k2g_vp_csc_cpr_regval()
2468 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); in dispc_k2g_vp_csc_cpr_regval()
2514 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); in dispc_S31_32_to_s3_8()
2526 cpr->to_regval = dispc_csc_cpr_regval; in dispc_csc_from_ctm()
2527 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); in dispc_csc_from_ctm()
2528 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); in dispc_csc_from_ctm()
2529 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); in dispc_csc_from_ctm()
2530 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); in dispc_csc_from_ctm()
2531 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); in dispc_csc_from_ctm()
2532 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); in dispc_csc_from_ctm()
2533 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); in dispc_csc_from_ctm()
2534 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); in dispc_csc_from_ctm()
2535 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); in dispc_csc_from_ctm()
2549 csc->to_regval(csc, regval); in dispc_k3_vp_write_csc()
2582 if (!(state->color_mgmt_changed || newmodeset)) in dispc_vp_set_color_mgmt()
2585 if (state->gamma_lut) { in dispc_vp_set_color_mgmt()
2586 lut = (struct drm_color_lut *)state->gamma_lut->data; in dispc_vp_set_color_mgmt()
2587 length = state->gamma_lut->length / sizeof(*lut); in dispc_vp_set_color_mgmt()
2592 if (state->ctm) in dispc_vp_set_color_mgmt()
2593 ctm = (struct drm_color_ctm *)state->ctm->data; in dispc_vp_set_color_mgmt()
2595 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2610 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2612 dispc->is_enabled = false; in dispc_runtime_suspend()
2614 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2621 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2623 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2626 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2628 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2631 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2636 if (dispc->feat->subrev == DISPC_AM625 || in dispc_runtime_resume()
2637 dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2638 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2643 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2648 dispc->is_enabled = true; in dispc_runtime_resume()
2650 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2657 dev_dbg(tidss->dev, "%s\n", __func__); in dispc_remove()
2659 tidss->dispc = NULL; in dispc_remove()
2669 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); in dispc_iomap_resource()
2681 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2682 syscon_regmap_lookup_by_phandle(dev->of_node, in dispc_init_am65x_oldi_io_ctrl()
2683 "ti,am65x-oldi-io-ctrl"); in dispc_init_am65x_oldi_io_ctrl()
2684 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2685 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2686 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2688 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2689 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2702 dispc->errata.i2000 = true; in dispc_init_errata()
2703 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2715 spin_lock_irqsave(&dispc->tidss->wait_lock, flags); in dispc_softreset_k2g()
2718 spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags); in dispc_softreset_k2g()
2720 for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx) in dispc_softreset_k2g()
2729 if (dispc->feat->subrev == DISPC_K2G) { in dispc_softreset()
2737 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, in dispc_softreset()
2740 dev_err(dispc->dev, "failed to reset dispc\n"); in dispc_softreset()
2749 struct device *dev = dispc->dev; in dispc_init_hw()
2754 dev_err(dev, "Failed to set DSS PM to active\n"); in dispc_init_hw()
2758 ret = clk_prepare_enable(dispc->fclk); in dispc_init_hw()
2760 dev_err(dev, "Failed to enable DSS fclk\n"); in dispc_init_hw()
2768 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2771 dev_err(dev, "Failed to set DSS PM to suspended\n"); in dispc_init_hw()
2778 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2783 dev_err(dev, "Failed to set DSS PM to suspended\n"); in dispc_init_hw()
2792 struct device *dev = tidss->dev; in dispc_init()
2801 feat = tidss->feat; in dispc_init()
2803 if (feat->subrev != DISPC_K2G) { in dispc_init()
2806 dev_warn(dev, "cannot set DMA masks to 48-bit\n"); in dispc_init()
2813 return -ENOMEM; in dispc_init()
2815 dispc->tidss = tidss; in dispc_init()
2816 dispc->dev = dev; in dispc_init()
2817 dispc->feat = feat; in dispc_init()
2821 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2822 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2823 if (!dispc->fourccs) in dispc_init()
2824 return -ENOMEM; in dispc_init()
2828 if (dispc->errata.i2000 && in dispc_init()
2832 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2835 dispc->num_fourccs = num_fourccs; in dispc_init()
2837 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2839 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2840 &dispc->base_common); in dispc_init()
2844 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2845 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2846 &dispc->base_vid[i]); in dispc_init()
2851 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2852 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2856 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2857 &dispc->base_ovr[i]); in dispc_init()
2861 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2862 &dispc->base_vp[i]); in dispc_init()
2866 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2869 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2872 dispc->vp_clk[i] = clk; in dispc_init()
2878 return -ENOMEM; in dispc_init()
2879 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2882 if (feat->subrev == DISPC_AM65X) { in dispc_init()
2888 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2889 if (IS_ERR(dispc->fclk)) { in dispc_init()
2891 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2892 return PTR_ERR(dispc->fclk); in dispc_init()
2894 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2896 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2897 &dispc->memory_bandwidth_limit); in dispc_init()
2903 tidss->dispc = dispc; in dispc_init()