387 	const u8 *lane_map;  member
656 		value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |  in tegra_sor_power_up_lanes()
657 			   SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));  in tegra_sor_power_up_lanes()
659 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |  in tegra_sor_power_up_lanes()
660 			 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);  in tegra_sor_power_up_lanes()
663 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);  in tegra_sor_power_up_lanes()
665 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);  in tegra_sor_power_up_lanes()
668 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);  in tegra_sor_power_up_lanes()
670 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);  in tegra_sor_power_up_lanes()
735 		value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |  in tegra_sor_dp_precharge()
736 			   SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));  in tegra_sor_dp_precharge()
738 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |  in tegra_sor_dp_precharge()
739 			 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);  in tegra_sor_dp_precharge()
742 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);  in tegra_sor_dp_precharge()
744 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);  in tegra_sor_dp_precharge()
747 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);  in tegra_sor_dp_precharge()
749 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);  in tegra_sor_dp_precharge()
814 		u8 shift = sor->soc->lane_map[i] << 3;  in tegra_sor_dp_link_apply_training()
3399 	.lane_map = tegra124_sor_lane_map,
3439 	.lane_map = tegra124_sor_lane_map,
3480 	.lane_map = tegra210_sor_lane_map,
3500 	.lane_map = tegra210_sor_lane_map,
3583 	.lane_map = tegra124_sor_lane_map,
3619 	.lane_map = tegra124_sor_lane_map,