Lines Matching refs:tegra_dsi_writel
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() function
367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); in tegra_dsi_set_phy_timing()
373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); in tegra_dsi_set_phy_timing()
378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); in tegra_dsi_set_phy_timing()
383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); in tegra_dsi_set_phy_timing()
448 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); in tegra_dsi_ganged_enable()
449 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); in tegra_dsi_ganged_enable()
452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); in tegra_dsi_ganged_enable()
461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_enable()
510 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_configure()
512 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); in tegra_dsi_configure()
515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_configure()
532 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_configure()
535 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); in tegra_dsi_configure()
558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); in tegra_dsi_configure()
559 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); in tegra_dsi_configure()
560 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); in tegra_dsi_configure()
561 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); in tegra_dsi_configure()
564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_dsi_configure()
580 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); in tegra_dsi_configure()
581 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); in tegra_dsi_configure()
582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); in tegra_dsi_configure()
583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); in tegra_dsi_configure()
587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); in tegra_dsi_configure()
608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); in tegra_dsi_configure()
647 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_video_disable()
655 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); in tegra_dsi_ganged_disable()
656 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); in tegra_dsi_ganged_disable()
657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); in tegra_dsi_ganged_disable()
665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); in tegra_dsi_pad_enable()
679 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); in tegra_dsi_pad_calibrate()
680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); in tegra_dsi_pad_calibrate()
681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); in tegra_dsi_pad_calibrate()
683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); in tegra_dsi_pad_calibrate()
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); in tegra_dsi_pad_calibrate()
713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); in tegra_dsi_set_timeout()
718 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); in tegra_dsi_set_timeout()
721 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); in tegra_dsi_set_timeout()
738 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_disable()
752 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
758 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
764 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); in tegra_dsi_soft_reset()
1279 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); in tegra_dsi_transmit()
1327 tegra_dsi_writel(dsi, value, DSI_WR_DATA); in tegra_dsi_writesl()
1355 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1361 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_host_transfer()
1378 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1388 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1392 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_host_transfer()
1396 tegra_dsi_writel(dsi, value, DSI_WR_DATA); in tegra_dsi_host_transfer()