Lines Matching refs:value
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl() local
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
113 return value; in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
119 trace_dsi_writel(dsi->dev, offset, value); in tegra_dsi_writel()
120 writel(value, dsi->regs + (offset << 2)); in tegra_dsi_writel()
361 u32 value; in tegra_dsi_set_phy_timing() local
363 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | in tegra_dsi_set_phy_timing()
367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); in tegra_dsi_set_phy_timing()
369 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | in tegra_dsi_set_phy_timing()
373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); in tegra_dsi_set_phy_timing()
375 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | in tegra_dsi_set_phy_timing()
378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); in tegra_dsi_set_phy_timing()
380 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | in tegra_dsi_set_phy_timing()
383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); in tegra_dsi_set_phy_timing()
446 u32 value; in tegra_dsi_ganged_enable() local
451 value = DSI_GANGED_MODE_CONTROL_ENABLE; in tegra_dsi_ganged_enable()
452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); in tegra_dsi_ganged_enable()
457 u32 value; in tegra_dsi_enable() local
459 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_enable()
460 value |= DSI_POWER_CONTROL_ENABLE; in tegra_dsi_enable()
461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_enable()
484 u32 value; in tegra_dsi_configure() local
506 value = DSI_CONTROL_CHANNEL(0) | in tegra_dsi_configure()
510 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_configure()
514 value = DSI_HOST_CONTROL_HS; in tegra_dsi_configure()
515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_configure()
517 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_dsi_configure()
520 value |= DSI_CONTROL_HS_CLK_CTRL; in tegra_dsi_configure()
522 value &= ~DSI_CONTROL_TX_TRIG(3); in tegra_dsi_configure()
526 value &= ~DSI_CONTROL_DCS_ENABLE; in tegra_dsi_configure()
528 value |= DSI_CONTROL_DCS_ENABLE; in tegra_dsi_configure()
530 value |= DSI_CONTROL_VIDEO_ENABLE; in tegra_dsi_configure()
531 value &= ~DSI_CONTROL_HOST_ENABLE; in tegra_dsi_configure()
532 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_configure()
585 value = MIPI_DCS_WRITE_MEMORY_START << 8 | in tegra_dsi_configure()
587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); in tegra_dsi_configure()
602 value = bclk - bclk_ganged + delay + 20; in tegra_dsi_configure()
605 value = 8 * mul / div; in tegra_dsi_configure()
608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); in tegra_dsi_configure()
626 u32 value; in tegra_dsi_wait_idle() local
631 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_wait_idle()
632 if (value & DSI_STATUS_IDLE) in tegra_dsi_wait_idle()
643 u32 value; in tegra_dsi_video_disable() local
645 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_dsi_video_disable()
646 value &= ~DSI_CONTROL_VIDEO_ENABLE; in tegra_dsi_video_disable()
647 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_video_disable()
662 u32 value; in tegra_dsi_pad_enable() local
664 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); in tegra_dsi_pad_enable()
665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); in tegra_dsi_pad_enable()
672 u32 value; in tegra_dsi_pad_calibrate() local
688 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | in tegra_dsi_pad_calibrate()
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
693 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | in tegra_dsi_pad_calibrate()
695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); in tegra_dsi_pad_calibrate()
708 u32 value; in tegra_dsi_set_timeout() local
712 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); in tegra_dsi_set_timeout()
713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); in tegra_dsi_set_timeout()
717 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); in tegra_dsi_set_timeout()
718 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); in tegra_dsi_set_timeout()
720 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); in tegra_dsi_set_timeout()
721 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); in tegra_dsi_set_timeout()
729 u32 value; in tegra_dsi_disable() local
736 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_disable()
737 value &= ~DSI_POWER_CONTROL_ENABLE; in tegra_dsi_disable()
738 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_disable()
748 u32 value; in tegra_dsi_soft_reset() local
750 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
751 value &= ~DSI_POWER_CONTROL_ENABLE; in tegra_dsi_soft_reset()
752 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
756 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
757 value |= DSI_POWER_CONTROL_ENABLE; in tegra_dsi_soft_reset()
758 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
762 value = tegra_dsi_readl(dsi, DSI_TRIGGER); in tegra_dsi_soft_reset()
763 if (value) in tegra_dsi_soft_reset()
846 u32 value; in tegra_dsi_encoder_disable() local
859 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
860 value &= ~DSI_ENABLE; in tegra_dsi_encoder_disable()
861 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
912 u32 value; in tegra_dsi_encoder_enable() local
919 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_encoder_enable()
921 if (value & DSI_POWER_CONTROL_ENABLE) in tegra_dsi_encoder_enable()
946 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()
947 value |= DSI_ENABLE; in tegra_dsi_encoder_enable()
948 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()
1220 u32 value; in tegra_dsi_read_response() local
1223 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_read_response()
1225 switch (value & 0x3f) { in tegra_dsi_read_response()
1227 errors = (value >> 8) & 0xffff; in tegra_dsi_read_response()
1237 rx[0] = (value >> 8) & 0xff; in tegra_dsi_read_response()
1242 rx[0] = (value >> 8) & 0xff; in tegra_dsi_read_response()
1243 rx[1] = (value >> 16) & 0xff; in tegra_dsi_read_response()
1248 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); in tegra_dsi_read_response()
1252 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); in tegra_dsi_read_response()
1257 value & 0x3f); in tegra_dsi_read_response()
1267 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_read_response()
1270 rx[j + k] = (value >> (k << 3)) & 0xff; in tegra_dsi_read_response()
1284 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); in tegra_dsi_transmit() local
1285 if ((value & DSI_TRIGGER_HOST) == 0) in tegra_dsi_transmit()
1301 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_wait_for_response() local
1302 u8 count = value & 0x1f; in tegra_dsi_wait_for_response()
1319 u32 value; in tegra_dsi_writesl() local
1322 value = 0; in tegra_dsi_writesl()
1325 value |= buf[j + i] << (i << 3); in tegra_dsi_writesl()
1327 tegra_dsi_writel(dsi, value, DSI_WR_DATA); in tegra_dsi_writesl()
1339 u32 value; in tegra_dsi_host_transfer() local
1352 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_host_transfer()
1353 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { in tegra_dsi_host_transfer()
1354 value = DSI_HOST_CONTROL_FIFO_RESET; in tegra_dsi_host_transfer()
1355 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1359 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_host_transfer()
1360 value |= DSI_POWER_CONTROL_ENABLE; in tegra_dsi_host_transfer()
1361 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_host_transfer()
1365 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | in tegra_dsi_host_transfer()
1369 value |= DSI_HOST_CONTROL_HS; in tegra_dsi_host_transfer()
1376 value |= DSI_HOST_CONTROL_FIFO_SEL; in tegra_dsi_host_transfer()
1378 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1386 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1387 value |= DSI_HOST_CONTROL_PKT_BTA; in tegra_dsi_host_transfer()
1388 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1391 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; in tegra_dsi_host_transfer()
1392 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_host_transfer()
1395 value = header[2] << 16 | header[1] << 8 | header[0]; in tegra_dsi_host_transfer()
1396 tegra_dsi_writel(dsi, value, DSI_WR_DATA); in tegra_dsi_host_transfer()
1415 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_host_transfer()
1416 switch (value) { in tegra_dsi_host_transfer()
1430 dev_err(dsi->dev, "unknown status: %08x\n", value); in tegra_dsi_host_transfer()