79 	u32 value = readl(dpaux->regs + (offset << 2));  in tegra_dpaux_readl()  local
81 	trace_dpaux_readl(dpaux->dev, offset, value);  in tegra_dpaux_readl()
83 	return value;  in tegra_dpaux_readl()
87 				      u32 value, unsigned int offset)  in tegra_dpaux_writel()  argument
89 	trace_dpaux_writel(dpaux->dev, offset, value);  in tegra_dpaux_writel()
90 	writel(value, dpaux->regs + (offset << 2));  in tegra_dpaux_writel()
100 		u32 value = 0;  in tegra_dpaux_write_fifo()  local
103 			value |= buffer[i * 4 + j] << (j * 8);  in tegra_dpaux_write_fifo()
105 		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));  in tegra_dpaux_write_fifo()
116 		u32 value;  in tegra_dpaux_read_fifo()  local
118 		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));  in tegra_dpaux_read_fifo()
121 			buffer[i * 4 + j] = value >> (j * 8);  in tegra_dpaux_read_fifo()
133 	u32 value;  in tegra_dpaux_transfer()  local
148 			value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;  in tegra_dpaux_transfer()
156 		value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);  in tegra_dpaux_transfer()
162 			value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;  in tegra_dpaux_transfer()
164 			value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;  in tegra_dpaux_transfer()
170 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;  in tegra_dpaux_transfer()
172 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;  in tegra_dpaux_transfer()
178 			value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;  in tegra_dpaux_transfer()
180 			value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;  in tegra_dpaux_transfer()
185 		value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;  in tegra_dpaux_transfer()
189 		value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;  in tegra_dpaux_transfer()
197 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
205 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
206 	value |= DPAUX_DP_AUXCTL_TRANSACTREQ;  in tegra_dpaux_transfer()
207 	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);  in tegra_dpaux_transfer()
214 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in tegra_dpaux_transfer()
217 	if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)  in tegra_dpaux_transfer()
220 	if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||  in tegra_dpaux_transfer()
221 	    (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||  in tegra_dpaux_transfer()
222 	    (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))  in tegra_dpaux_transfer()
225 	switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {  in tegra_dpaux_transfer()
249 			size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;  in tegra_dpaux_transfer()
283 	u32 value;  in tegra_dpaux_irq()  local
286 	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
287 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_irq()
289 	if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))  in tegra_dpaux_irq()
292 	if (value & DPAUX_INTR_IRQ_EVENT) {  in tegra_dpaux_irq()
296 	if (value & DPAUX_INTR_AUX_DONE)  in tegra_dpaux_irq()
310 	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_down()  local
312 	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_pad_power_down()
314 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_down()
319 	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_up()  local
321 	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;  in tegra_dpaux_pad_power_up()
323 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);  in tegra_dpaux_pad_power_up()
328 	u32 value;  in tegra_dpaux_pad_config()  local
332 		value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |  in tegra_dpaux_pad_config()
340 		value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |  in tegra_dpaux_pad_config()
356 	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);  in tegra_dpaux_pad_config()
450 	u32 value;  in tegra_dpaux_probe()  local
563 	value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |  in tegra_dpaux_probe()
565 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);  in tegra_dpaux_probe()
566 	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);  in tegra_dpaux_probe()
803 	u32 value;  in drm_dp_aux_detect()  local
805 	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);  in drm_dp_aux_detect()
807 	if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)  in drm_dp_aux_detect()