Lines Matching +full:layer +full:- +full:alpha +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
90 /* for DE2 VI layer which ignores alpha */
99 /* for DE2 VI layer which ignores alpha */
108 /* for DE2 VI layer which ignores alpha */
117 /* for DE2 VI layer which ignores alpha */
126 /* for DE2 VI layer which ignores alpha */
135 /* for DE2 VI layer which ignores alpha */
144 /* for DE2 VI layer which ignores alpha */
153 /* for DE2 VI layer which ignores alpha */
249 return -EINVAL; in sun8i_mixer_drm_format_to_hw()
256 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, in sun8i_mixer_commit()
267 planes = devm_kcalloc(drm->dev, in sun8i_layers_init()
268 mixer->cfg->vi_num + mixer->cfg->ui_num + 1, in sun8i_layers_init()
271 return ERR_PTR(-ENOMEM); in sun8i_layers_init()
273 for (i = 0; i < mixer->cfg->vi_num; i++) { in sun8i_layers_init()
274 struct sun8i_vi_layer *layer; in sun8i_layers_init() local
276 layer = sun8i_vi_layer_init_one(drm, mixer, i); in sun8i_layers_init()
277 if (IS_ERR(layer)) { in sun8i_layers_init()
278 dev_err(drm->dev, in sun8i_layers_init()
280 return ERR_CAST(layer); in sun8i_layers_init()
283 planes[i] = &layer->plane; in sun8i_layers_init()
286 for (i = 0; i < mixer->cfg->ui_num; i++) { in sun8i_layers_init()
287 struct sun8i_ui_layer *layer; in sun8i_layers_init() local
289 layer = sun8i_ui_layer_init_one(drm, mixer, i); in sun8i_layers_init()
290 if (IS_ERR(layer)) { in sun8i_layers_init()
291 dev_err(drm->dev, "Couldn't initialize %s plane\n", in sun8i_layers_init()
293 return ERR_CAST(layer); in sun8i_layers_init()
296 planes[mixer->cfg->vi_num + i] = &layer->plane; in sun8i_layers_init()
303 const struct drm_display_mode *mode) in sun8i_mixer_mode_set() argument
310 interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); in sun8i_mixer_mode_set()
311 size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); in sun8i_mixer_mode_set()
314 mode->hdisplay, mode->vdisplay); in sun8i_mixer_mode_set()
316 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size); in sun8i_mixer_mode_set()
317 regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); in sun8i_mixer_mode_set()
324 regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), in sun8i_mixer_mode_set()
327 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", in sun8i_mixer_mode_set()
350 ep = of_graph_get_endpoint_by_regs(node, 1, -1); in sun8i_mixer_of_get_id()
352 return -EINVAL; in sun8i_mixer_of_get_id()
357 return -EINVAL; in sun8i_mixer_of_get_id()
369 struct sun4i_drv *drv = drm->dev_private; in sun8i_mixer_bind()
377 * The mixer uses single 32-bit register to store memory in sun8i_mixer_bind()
378 * addresses, so that it cannot deal with 64-bit memory in sun8i_mixer_bind()
385 dev_err(dev, "Cannot do 32-bit DMA.\n"); in sun8i_mixer_bind()
391 return -ENOMEM; in sun8i_mixer_bind()
393 mixer->engine.ops = &sun8i_engine_ops; in sun8i_mixer_bind()
394 mixer->engine.node = dev->of_node; in sun8i_mixer_bind()
396 if (of_property_present(dev->of_node, "iommus")) { in sun8i_mixer_bind()
401 * DRM doesn't do per-device allocation either, so we in sun8i_mixer_bind()
404 ret = of_dma_configure(drm->dev, dev->of_node, true); in sun8i_mixer_bind()
417 mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node); in sun8i_mixer_bind()
419 mixer->cfg = of_device_get_match_data(dev); in sun8i_mixer_bind()
420 if (!mixer->cfg) in sun8i_mixer_bind()
421 return -EINVAL; in sun8i_mixer_bind()
427 mixer->engine.regs = devm_regmap_init_mmio(dev, regs, in sun8i_mixer_bind()
429 if (IS_ERR(mixer->engine.regs)) { in sun8i_mixer_bind()
431 return PTR_ERR(mixer->engine.regs); in sun8i_mixer_bind()
434 mixer->reset = devm_reset_control_get(dev, NULL); in sun8i_mixer_bind()
435 if (IS_ERR(mixer->reset)) { in sun8i_mixer_bind()
437 return PTR_ERR(mixer->reset); in sun8i_mixer_bind()
440 ret = reset_control_deassert(mixer->reset); in sun8i_mixer_bind()
446 mixer->bus_clk = devm_clk_get(dev, "bus"); in sun8i_mixer_bind()
447 if (IS_ERR(mixer->bus_clk)) { in sun8i_mixer_bind()
449 ret = PTR_ERR(mixer->bus_clk); in sun8i_mixer_bind()
452 clk_prepare_enable(mixer->bus_clk); in sun8i_mixer_bind()
454 mixer->mod_clk = devm_clk_get(dev, "mod"); in sun8i_mixer_bind()
455 if (IS_ERR(mixer->mod_clk)) { in sun8i_mixer_bind()
457 ret = PTR_ERR(mixer->mod_clk); in sun8i_mixer_bind()
466 if (mixer->cfg->mod_rate) in sun8i_mixer_bind()
467 clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate); in sun8i_mixer_bind()
469 clk_prepare_enable(mixer->mod_clk); in sun8i_mixer_bind()
471 list_add_tail(&mixer->engine.list, &drv->engine_list); in sun8i_mixer_bind()
475 /* Reset registers and disable unused sub-engines */ in sun8i_mixer_bind()
476 if (mixer->cfg->is_de3) { in sun8i_mixer_bind()
478 regmap_write(mixer->engine.regs, i, 0); in sun8i_mixer_bind()
480 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0); in sun8i_mixer_bind()
481 regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0); in sun8i_mixer_bind()
482 regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0); in sun8i_mixer_bind()
483 regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0); in sun8i_mixer_bind()
484 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0); in sun8i_mixer_bind()
485 regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0); in sun8i_mixer_bind()
486 regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0); in sun8i_mixer_bind()
487 regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0); in sun8i_mixer_bind()
488 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0); in sun8i_mixer_bind()
489 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0); in sun8i_mixer_bind()
492 regmap_write(mixer->engine.regs, i, 0); in sun8i_mixer_bind()
494 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0); in sun8i_mixer_bind()
495 regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0); in sun8i_mixer_bind()
496 regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0); in sun8i_mixer_bind()
497 regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0); in sun8i_mixer_bind()
498 regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0); in sun8i_mixer_bind()
499 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0); in sun8i_mixer_bind()
500 regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); in sun8i_mixer_bind()
504 regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, in sun8i_mixer_bind()
508 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), in sun8i_mixer_bind()
515 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), in sun8i_mixer_bind()
517 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), in sun8i_mixer_bind()
520 plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; in sun8i_mixer_bind()
522 regmap_write(mixer->engine.regs, in sun8i_mixer_bind()
526 regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), in sun8i_mixer_bind()
532 clk_disable_unprepare(mixer->bus_clk); in sun8i_mixer_bind()
534 reset_control_assert(mixer->reset); in sun8i_mixer_bind()
543 list_del(&mixer->engine.list); in sun8i_mixer_unbind()
545 clk_disable_unprepare(mixer->mod_clk); in sun8i_mixer_unbind()
546 clk_disable_unprepare(mixer->bus_clk); in sun8i_mixer_unbind()
547 reset_control_assert(mixer->reset); in sun8i_mixer_unbind()
557 return component_add(&pdev->dev, &sun8i_mixer_ops); in sun8i_mixer_probe()
562 component_del(&pdev->dev, &sun8i_mixer_ops); in sun8i_mixer_remove()
665 .compatible = "allwinner,sun8i-a83t-de2-mixer-0",
669 .compatible = "allwinner,sun8i-a83t-de2-mixer-1",
673 .compatible = "allwinner,sun8i-h3-de2-mixer-0",
677 .compatible = "allwinner,sun8i-r40-de2-mixer-0",
681 .compatible = "allwinner,sun8i-r40-de2-mixer-1",
685 .compatible = "allwinner,sun8i-v3s-de2-mixer",
689 .compatible = "allwinner,sun20i-d1-de2-mixer-0",
693 .compatible = "allwinner,sun20i-d1-de2-mixer-1",
697 .compatible = "allwinner,sun50i-a64-de2-mixer-0",
701 .compatible = "allwinner,sun50i-a64-de2-mixer-1",
705 .compatible = "allwinner,sun50i-h6-de3-mixer-0",
716 .name = "sun8i-mixer",