Lines Matching defs:sun4i_hdmi_variant

196 struct sun4i_hdmi_variant {  struct
197 	bool has_ddc_parent_clk;
198 	bool has_reset_control;
200 	u32 pad_ctrl0_init_val;
201 	u32 pad_ctrl1_init_val;
202 	u32 pll_ctrl_init_val;
204 	struct reg_field ddc_clk_reg;
205 	u8 ddc_clk_pre_divider;
206 	u8 ddc_clk_m_offset;
208 	u8 tmds_clk_div_offset;
211 	struct reg_field	field_ddc_en;
212 	struct reg_field	field_ddc_start;
213 	struct reg_field	field_ddc_reset;
214 	struct reg_field	field_ddc_addr_reg;
215 	struct reg_field	field_ddc_slave_addr;
216 	struct reg_field	field_ddc_int_mask;
217 	struct reg_field	field_ddc_int_status;
218 	struct reg_field	field_ddc_fifo_clear;
219 	struct reg_field	field_ddc_fifo_rx_thres;
220 	struct reg_field	field_ddc_fifo_tx_thres;
221 	struct reg_field	field_ddc_byte_count;
222 	struct reg_field	field_ddc_cmd;
223 	struct reg_field	field_ddc_sda_en;
224 	struct reg_field	field_ddc_sck_en;
227 	u32			ddc_fifo_reg;
240 	bool			ddc_fifo_thres_incl;
242 	bool			ddc_fifo_has_dir;