Lines Matching +full:0 +full:xffff
84 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
85 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
86 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
87 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
91 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
92 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
100 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
101 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
102 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
103 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
104 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
105 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
106 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
107 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
108 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
109 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
110 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
111 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
112 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
120 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
121 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
122 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
123 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
124 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
125 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
126 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
127 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
128 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
129 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
130 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
134 { .base = 0x00, .phy = &rk3036_win0_data,
136 { .base = 0x00, .phy = &rk3036_win1_data,
150 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
151 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0),
152 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4),
153 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8),
157 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
158 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
159 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
160 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
164 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
168 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
169 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
170 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
171 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
172 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
173 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
174 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
191 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
192 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
193 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
194 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
195 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
196 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
197 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
198 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
199 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
200 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
204 { .base = 0x00, .phy = &rk3036_win0_data,
206 { .base = 0x00, .phy = &rk3126_win1_data,
222 0, 0,
224 0,
226 0, 0,
233 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0),
234 .status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0),
235 .enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0),
236 .clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0),
240 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1),
241 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16),
242 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14),
243 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8),
244 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7),
245 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6),
246 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0),
250 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
251 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0),
252 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
253 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0),
257 .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1),
258 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2),
259 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0),
260 .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25),
261 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26),
262 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24),
266 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
267 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
268 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
269 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
277 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0),
278 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1),
279 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12),
280 .uv_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 15),
281 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0),
282 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0),
283 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0),
284 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0),
285 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0),
286 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0),
287 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16),
288 .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2),
289 .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1),
290 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
297 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0),
298 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4),
299 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12),
300 .uv_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 15),
301 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0),
302 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0),
303 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0),
304 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0),
305 .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2),
306 .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1),
307 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
314 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4),
315 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0),
316 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5),
317 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20),
318 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0),
319 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0),
320 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0),
321 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0),
322 .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2),
323 .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1),
324 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
328 { .base = 0x00, .phy = &px30_win0_data,
330 { .base = 0x00, .phy = &px30_win1_data,
332 { .base = 0x00, .phy = &px30_win2_data,
349 { .base = 0x00, .phy = &px30_win1_data,
366 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
367 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
368 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
369 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
377 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
378 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 4),
379 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 19),
380 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 22),
381 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
382 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
383 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
384 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
385 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
386 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
387 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
388 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),
389 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0),
396 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
397 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 7),
398 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 23),
399 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 26),
400 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
401 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
402 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
403 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
404 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
405 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
406 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
407 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),
408 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1),
415 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
416 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 10),
417 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 27),
418 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
419 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
420 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
421 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
422 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),
423 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2),
427 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
428 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
429 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
430 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
434 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
438 .dma_stop = VOP_REG(RK3066_SYS_CTRL0, 0x1, 0),
439 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
440 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
441 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
442 .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11),
443 .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10),
444 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
445 .dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9),
446 .dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31),
447 .data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25),
451 { .base = 0x00, .phy = &rk3066_win0_data,
453 { .base = 0x00, .phy = &rk3066_win1_data,
455 { .base = 0x00, .phy = &rk3066_win2_data,
473 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
474 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
475 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
476 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
492 .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
493 .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
494 .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
495 .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
503 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0),
504 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3),
505 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15),
506 .uv_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 18),
507 .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0),
508 .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0),
509 .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0),
510 .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0),
511 .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0),
512 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0),
513 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18),
514 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0),
515 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29),
522 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1),
523 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6),
524 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19),
526 .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0),
527 .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0),
528 .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0),
529 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16),
530 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19),
531 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 1),
532 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29),
536 .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
537 .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0),
538 .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
539 .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0),
543 .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
547 .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31),
548 .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30),
549 .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0),
550 .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0),
551 .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27),
552 .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11),
553 .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10),
554 .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 24),
555 .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
556 .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
557 .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
561 { .base = 0x00, .phy = &rk3188_win0_data,
563 { .base = 0x00, .phy = &rk3188_win1_data,
581 .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12),
582 .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0),
583 .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4),
584 .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8),
599 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
600 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
601 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
602 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
603 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
604 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
605 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
606 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
607 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
608 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
609 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
610 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
611 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
612 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
613 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
614 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
615 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
616 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
617 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
618 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
619 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
624 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
625 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
626 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
627 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
635 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
636 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
637 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
638 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
639 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
640 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
641 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
642 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
643 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
644 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
645 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
646 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
647 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
648 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
655 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
656 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
657 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
658 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
659 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
660 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
661 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
662 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
663 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
664 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
668 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
669 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
670 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
671 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
672 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
673 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
677 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
678 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
679 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
680 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
681 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
685 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
686 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
687 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
688 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
689 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
690 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
691 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
692 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
693 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
694 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
695 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
696 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
697 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
707 { .base = 0x00, .phy = &rk3288_win01_data,
709 { .base = 0x40, .phy = &rk3288_win01_data,
711 { .base = 0x00, .phy = &rk3288_win23_data,
713 { .base = 0x50, .phy = &rk3288_win23_data,
727 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
728 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
729 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
730 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
753 0, 0,
755 0,
757 0, 0, 0, 0, 0, 0, 0,
764 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
765 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
766 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
767 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
768 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
776 .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
777 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
778 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
779 .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15),
780 .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
781 .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
782 .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0),
783 .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0),
784 .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0),
785 .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0),
786 .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0),
787 .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0),
788 .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16),
789 .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
790 .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0),
791 .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0),
798 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
799 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
800 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
801 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
802 .y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
803 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
804 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
805 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
806 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
807 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
808 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
812 { .base = 0x00, .phy = &rk3368_win01_data,
814 { .base = 0x40, .phy = &rk3368_win01_data,
816 { .base = 0x00, .phy = &rk3368_win23_data,
818 { .base = 0x50, .phy = &rk3368_win23_data,
823 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
824 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
825 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
826 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
827 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
828 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
829 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
830 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
831 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
832 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
833 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
834 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
838 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11),
856 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
857 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
858 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0),
859 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0),
860 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0),
876 .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
877 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
878 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
879 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
880 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
881 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
882 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
883 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
884 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
885 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
886 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
887 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
888 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
889 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
890 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
891 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
895 .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
896 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
897 .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20),
898 .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4),
899 .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3),
900 .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2),
901 .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1),
902 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
903 .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0),
904 .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7),
905 .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1),
906 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
907 .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
908 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
909 .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
914 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
915 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16),
916 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0),
917 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16),
918 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0),
919 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16),
920 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0),
921 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16),
922 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0),
923 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0),
924 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0),
925 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0),
932 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
933 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) },
934 { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data,
935 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) },
936 { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data },
937 { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data },
946 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
947 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
948 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
949 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
950 .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
951 .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
952 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
953 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
954 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
955 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
956 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
957 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
958 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
959 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
960 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
961 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
970 { .base = 0x00, .phy = &rk3399_win01_data,
972 { .base = 0x40, .phy = &rk3368_win01_data,
974 { .base = 0x00, .phy = &rk3368_win23_data,
976 { .base = 0x50, .phy = &rk3368_win23_data,
981 .rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
982 .enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
983 .win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
984 .format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
985 .hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
986 .hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
987 .pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
1007 { .base = 0x00, .phy = &rk3368_win01_data,
1009 { .base = 0x00, .phy = &rk3368_win23_data,
1014 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
1015 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)},
1016 { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data },
1034 { .base = 0x00, .phy = &rk3288_win01_data,
1036 { .base = 0x40, .phy = &rk3288_win01_data,
1054 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1055 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
1056 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1057 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
1058 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1059 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1063 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
1064 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
1065 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
1066 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
1067 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
1068 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
1069 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
1070 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
1071 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
1072 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
1073 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
1074 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
1078 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
1082 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22),
1083 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
1084 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
1085 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
1086 .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
1087 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
1088 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
1089 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
1090 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
1096 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
1097 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
1098 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0),
1099 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0),
1100 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0),
1104 { .base = 0xd0, .phy = &rk3368_win01_data,
1106 { .base = 0x1d0, .phy = &rk3368_win01_data,
1108 { .base = 0x2d0, .phy = &rk3368_win01_data,