Lines Matching refs:vp
246 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) in vop2_vp_write() argument
248 regmap_write(vp->vop2->map, vp->data->offset + offset, v); in vop2_vp_write()
270 static void vop2_cfg_done(struct vop2_video_port *vp) in vop2_cfg_done() argument
272 struct vop2 *vop2 = vp->vop2; in vop2_cfg_done()
275 BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); in vop2_cfg_done()
756 static void vop2_setup_csc_mode(struct vop2_video_port *vp, in vop2_setup_csc_mode() argument
760 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); in vop2_setup_csc_mode()
787 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) in vop2_crtc_enable_irq() argument
789 struct vop2 *vop2 = vp->vop2; in vop2_crtc_enable_irq()
791 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); in vop2_crtc_enable_irq()
792 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); in vop2_crtc_enable_irq()
795 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) in vop2_crtc_disable_irq() argument
797 struct vop2 *vop2 = vp->vop2; in vop2_crtc_disable_irq()
799 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); in vop2_crtc_disable_irq()
886 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_disable() local
887 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_disable()
905 reinit_completion(&vp->dsp_hold_completion); in vop2_crtc_atomic_disable()
907 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); in vop2_crtc_atomic_disable()
909 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); in vop2_crtc_atomic_disable()
911 ret = wait_for_completion_timeout(&vp->dsp_hold_completion, in vop2_crtc_atomic_disable()
914 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); in vop2_crtc_atomic_disable()
916 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); in vop2_crtc_atomic_disable()
918 clk_disable_unprepare(vp->dclk); in vop2_crtc_atomic_disable()
943 struct vop2_video_port *vp; in vop2_plane_atomic_check() local
956 vp = to_vop2_video_port(crtc); in vop2_plane_atomic_check()
957 vop2 = vp->vop2; in vop2_plane_atomic_check()
1082 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_plane_atomic_update() local
1156 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); in vop2_plane_atomic_update()
1167 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); in vop2_plane_atomic_update()
1181 vp->id, win->data->name, actual_w); in vop2_plane_atomic_update()
1188 vp->id, win->data->name, actual_w); in vop2_plane_atomic_update()
1198 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, in vop2_plane_atomic_update()
1222 vp->id, win->data->name, stride); in vop2_plane_atomic_update()
1296 vop2_setup_csc_mode(vp, win, pstate); in vop2_plane_atomic_update()
1329 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_enable_vblank() local
1331 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); in vop2_crtc_enable_vblank()
1338 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_disable_vblank() local
1340 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); in vop2_crtc_disable_vblank()
1384 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_post_config() local
1404 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); in vop2_post_config()
1409 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); in vop2_post_config()
1412 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); in vop2_post_config()
1419 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); in vop2_post_config()
1426 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); in vop2_post_config()
1429 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); in vop2_post_config()
1432 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, in rk3568_set_intf_mux() argument
1435 struct vop2 *vop2 = vp->vop2; in rk3568_set_intf_mux()
1445 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); in rk3568_set_intf_mux()
1456 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); in rk3568_set_intf_mux()
1463 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); in rk3568_set_intf_mux()
1470 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); in rk3568_set_intf_mux()
1477 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); in rk3568_set_intf_mux()
1484 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); in rk3568_set_intf_mux()
1491 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); in rk3568_set_intf_mux()
1496 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); in rk3568_set_intf_mux()
1514 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_enable() local
1515 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_enable()
1517 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; in vop2_crtc_atomic_enable()
1541 drm_mode_vrefresh(mode), vcstate->output_type, vp->id); in vop2_crtc_atomic_enable()
1545 ret = clk_prepare_enable(vp->dclk); in vop2_crtc_atomic_enable()
1548 vp->id, ret); in vop2_crtc_atomic_enable()
1558 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); in vop2_crtc_atomic_enable()
1571 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); in vop2_crtc_atomic_enable()
1590 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); in vop2_crtc_atomic_enable()
1593 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); in vop2_crtc_atomic_enable()
1597 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); in vop2_crtc_atomic_enable()
1604 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); in vop2_crtc_atomic_enable()
1607 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); in vop2_crtc_atomic_enable()
1617 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), in vop2_crtc_atomic_enable()
1620 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); in vop2_crtc_atomic_enable()
1627 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); in vop2_crtc_atomic_enable()
1629 clk_set_rate(vp->dclk, clock); in vop2_crtc_atomic_enable()
1633 vop2_cfg_done(vp); in vop2_crtc_atomic_enable()
1635 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); in vop2_crtc_atomic_enable()
1645 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_check() local
1653 if (nplanes > vp->nlayers) in vop2_crtc_atomic_check()
1725 struct vop2_video_port *vp; in vop2_find_start_mixer_id_for_vp() local
1730 vp = &vop2->vps[i]; in vop2_find_start_mixer_id_for_vp()
1731 used_layer += hweight32(vp->win_mask); in vop2_find_start_mixer_id_for_vp()
1775 static void vop2_setup_alpha(struct vop2_video_port *vp) in vop2_setup_alpha() argument
1777 struct vop2 *vop2 = vp->vop2; in vop2_setup_alpha()
1789 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); in vop2_setup_alpha()
1792 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { in vop2_setup_alpha()
1808 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { in vop2_setup_alpha()
1858 if (vp->id == 0) { in vop2_setup_alpha()
1882 static void vop2_setup_layer_mixer(struct vop2_video_port *vp) in vop2_setup_layer_mixer() argument
1884 struct vop2 *vop2 = vp->vop2; in vop2_setup_layer_mixer()
1899 adjusted_mode = &vp->crtc.state->adjusted_mode; in vop2_setup_layer_mixer()
1903 bg_dly = vp->data->pre_scan_max_dly[3]; in vop2_setup_layer_mixer()
1904 vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), in vop2_setup_layer_mixer()
1908 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); in vop2_setup_layer_mixer()
1935 for (i = 0; i < vp->id; i++) in vop2_setup_layer_mixer()
1939 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { in vop2_setup_layer_mixer()
1945 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); in vop2_setup_layer_mixer()
1949 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); in vop2_setup_layer_mixer()
1953 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); in vop2_setup_layer_mixer()
1957 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); in vop2_setup_layer_mixer()
1961 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); in vop2_setup_layer_mixer()
1965 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); in vop2_setup_layer_mixer()
1977 for (; nlayer < vp->nlayers; nlayer++) { in vop2_setup_layer_mixer()
2030 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_begin() local
2031 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_begin()
2034 vp->win_mask = 0; in vop2_crtc_atomic_begin()
2041 vp->win_mask |= BIT(win->data->phys_id); in vop2_crtc_atomic_begin()
2047 if (!vp->win_mask) in vop2_crtc_atomic_begin()
2050 vop2_setup_layer_mixer(vp); in vop2_crtc_atomic_begin()
2051 vop2_setup_alpha(vp); in vop2_crtc_atomic_begin()
2058 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_flush() local
2062 vop2_cfg_done(vp); in vop2_crtc_atomic_flush()
2068 vp->event = crtc->state->event; in vop2_crtc_atomic_flush()
2151 struct vop2_video_port *vp = &vop2->vps[i]; in vop2_isr() local
2152 struct drm_crtc *crtc = &vp->crtc; in vop2_isr()
2155 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); in vop2_isr()
2156 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); in vop2_isr()
2159 complete(&vp->dsp_hold_completion); in vop2_isr()
2166 if (vp->event) { in vop2_isr()
2169 if (!(val & BIT(vp->id))) { in vop2_isr()
2170 drm_crtc_send_vblank_event(crtc, vp->event); in vop2_isr()
2171 vp->event = NULL; in vop2_isr()
2183 vp->id); in vop2_isr()
2243 struct vop2_video_port *vp = &vop2->vps[i]; in find_vp_without_primary() local
2245 if (!vp->crtc.port) in find_vp_without_primary()
2247 if (vp->primary_plane) in find_vp_without_primary()
2250 return vp; in find_vp_without_primary()
2265 struct vop2_video_port *vp; in vop2_create_crtcs() local
2274 vp_data = &vop2_data->vp[i]; in vop2_create_crtcs()
2275 vp = &vop2->vps[i]; in vop2_create_crtcs()
2276 vp->vop2 = vop2; in vop2_create_crtcs()
2277 vp->id = vp_data->id; in vop2_create_crtcs()
2278 vp->regs = vp_data->regs; in vop2_create_crtcs()
2279 vp->data = vp_data; in vop2_create_crtcs()
2281 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); in vop2_create_crtcs()
2282 vp->dclk = devm_clk_get(vop2->dev, dclk_name); in vop2_create_crtcs()
2283 if (IS_ERR(vp->dclk)) { in vop2_create_crtcs()
2285 return PTR_ERR(vp->dclk); in vop2_create_crtcs()
2301 vp->crtc.port = port; in vop2_create_crtcs()
2325 vp = find_vp_without_primary(vop2); in vop2_create_crtcs()
2326 if (vp) { in vop2_create_crtcs()
2328 vp->primary_plane = win; in vop2_create_crtcs()
2348 vp = &vop2->vps[i]; in vop2_create_crtcs()
2350 if (!vp->crtc.port) in vop2_create_crtcs()
2353 plane = &vp->primary_plane->base; in vop2_create_crtcs()
2355 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, in vop2_create_crtcs()
2357 "video_port%d", vp->id); in vop2_create_crtcs()
2363 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); in vop2_create_crtcs()
2365 init_completion(&vp->dsp_hold_completion); in vop2_create_crtcs()
2374 struct vop2_video_port *vp = &vop2->vps[i]; in vop2_create_crtcs() local
2376 if (vp->crtc.port) in vop2_create_crtcs()
2377 vp->nlayers = NR_LAYERS / nvps; in vop2_create_crtcs()