Lines Matching refs:vop2_vp_write
246 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
909 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
1404 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1409 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1412 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1419 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1426 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1429 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1590 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
1593 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
1597 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
1604 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
1607 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
1620 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
1627 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
1635 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1908 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);