Lines Matching refs:vop2
34 #include <dt-bindings/soc/rockchip,vop2.h>
142 struct vop2 *vop2;
160 struct vop2 *vop2;
179 struct vop2 {
196 /* physical map length of vop2 register */
231 static void vop2_lock(struct vop2 *vop2)
233 mutex_lock(&vop2->vop2_lock);
236 static void vop2_unlock(struct vop2 *vop2)
238 mutex_unlock(&vop2->vop2_lock);
241 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
243 regmap_write(vop2->map, offset, v);
248 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
251 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
255 regmap_read(vop2->map, offset, &val);
272 struct vop2 *vop2 = vp->vop2;
274 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
463 struct vop2 *vop2 = win->vop2;
472 drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n",
605 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
647 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
789 struct vop2 *vop2 = vp->vop2;
791 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
792 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
797 struct vop2 *vop2 = vp->vop2;
799 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
802 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
806 ret = clk_prepare_enable(vop2->hclk);
808 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
812 ret = clk_prepare_enable(vop2->aclk);
814 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
820 clk_disable_unprepare(vop2->hclk);
825 static void vop2_enable(struct vop2 *vop2)
829 ret = pm_runtime_resume_and_get(vop2->dev);
831 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
835 ret = vop2_core_clks_prepare_enable(vop2);
837 pm_runtime_put_sync(vop2->dev);
841 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
843 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
847 regcache_sync(vop2->map);
849 if (vop2->data->soc_id == 3566)
850 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
852 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
858 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
861 vop2_writel(vop2, RK3568_SYS0_INT_CLR,
863 vop2_writel(vop2, RK3568_SYS0_INT_EN,
865 vop2_writel(vop2, RK3568_SYS1_INT_CLR,
867 vop2_writel(vop2, RK3568_SYS1_INT_EN,
871 static void vop2_disable(struct vop2 *vop2)
873 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
875 pm_runtime_put_sync(vop2->dev);
877 regcache_mark_dirty(vop2->map);
879 clk_disable_unprepare(vop2->aclk);
880 clk_disable_unprepare(vop2->hclk);
887 struct vop2 *vop2 = vp->vop2;
891 vop2_lock(vop2);
914 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
920 vop2->enable_count--;
922 if (!vop2->enable_count)
923 vop2_disable(vop2);
925 vop2_unlock(vop2);
944 struct vop2 *vop2;
957 vop2 = vp->vop2;
958 vop2_data = vop2->data;
979 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
988 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
1001 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1013 struct vop2 *vop2 = win->vop2;
1015 drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1084 struct vop2 *vop2 = win->vop2;
1109 * can't update plane when vop2 is disabled.
1155 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1166 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1180 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1187 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1197 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1221 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1289 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1435 struct vop2 *vop2 = vp->vop2;
1438 die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1439 dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1449 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1451 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1496 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1502 vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1503 vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1515 struct vop2 *vop2 = vp->vop2;
1516 const struct vop2_data *vop2_data = vop2->data;
1539 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1543 vop2_lock(vop2);
1547 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1549 vop2_unlock(vop2);
1553 if (!vop2->enable_count)
1554 vop2_enable(vop2);
1556 vop2->enable_count++;
1617 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
1639 vop2_unlock(vop2);
1723 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
1730 vp = &vop2->vps[i];
1737 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
1765 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
1767 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
1769 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
1771 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
1777 struct vop2 *vop2 = vp->vop2;
1789 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
1848 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
1850 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
1852 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
1854 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
1868 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
1870 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
1872 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
1874 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
1877 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
1884 struct vop2 *vop2 = vp->vop2;
1895 struct vop2_video_port *vp0 = &vop2->vps[0];
1896 struct vop2_video_port *vp1 = &vop2->vps[1];
1897 struct vop2_video_port *vp2 = &vop2->vps[2];
1904 vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1910 vop2_writel(vop2, RK3568_OVL_CTRL, 0);
1911 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
1932 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
1936 ofs += vop2->vps[i].nlayers;
1982 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
1983 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
1984 vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD);
1987 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
1993 for (i = 0; i < vop2->data->win_size; i++) {
1996 win = &vop2->win[i];
2023 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2024 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2031 struct vop2 *vop2 = vp->vop2;
2044 vop2_setup_cluster_alpha(vop2, win);
2052 vop2_setup_dly_for_windows(vop2);
2137 struct vop2 *vop2 = data;
2138 const struct vop2_data *vop2_data = vop2->data;
2145 * vop2-device is disabled the irq has to be targeted at the iommu.
2147 if (!pm_runtime_get_if_in_use(vop2->dev))
2151 struct vop2_video_port *vp = &vop2->vps[i];
2155 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2156 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2167 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2181 drm_err_ratelimited(vop2->drm,
2188 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2189 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2190 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2191 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2195 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2200 pm_runtime_put(vop2->dev);
2205 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2214 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2220 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2233 vop2->registered_num_wins - 1);
2238 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2242 for (i = 0; i < vop2->data->nr_vps; i++) {
2243 struct vop2_video_port *vp = &vop2->vps[i];
2258 static int vop2_create_crtcs(struct vop2 *vop2)
2260 const struct vop2_data *vop2_data = vop2->data;
2261 struct drm_device *drm = vop2->drm;
2262 struct device *dev = vop2->dev;
2275 vp = &vop2->vps[i];
2276 vp->vop2 = vop2;
2282 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2284 drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2290 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2297 drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2306 for (i = 0; i < vop2->registered_num_wins; i++) {
2307 struct vop2_win *win = &vop2->win[i];
2310 if (vop2->data->soc_id == 3566) {
2325 vp = find_vp_without_primary(vop2);
2339 ret = vop2_plane_init(vop2, win, possible_crtcs);
2341 drm_err(vop2->drm, "failed to init plane %s: %d\n",
2348 vp = &vop2->vps[i];
2359 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2373 for (i = 0; i < vop2->data->nr_vps; i++) {
2374 struct vop2_video_port *vp = &vop2->vps[i];
2383 static void vop2_destroy_crtcs(struct vop2 *vop2)
2385 struct drm_device *drm = vop2->drm;
2404 static int vop2_find_rgb_encoder(struct vop2 *vop2)
2406 struct device_node *node = vop2->dev->of_node;
2410 for (i = 0; i < vop2->data->nr_vps; i++) {
2489 struct vop2 *vop2 = win->vop2;
2502 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2573 struct vop2 *vop2 = win->vop2;
2586 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2595 static int vop2_win_init(struct vop2 *vop2)
2597 const struct vop2_data *vop2_data = vop2->data;
2604 win = &vop2->win[i];
2609 win->vop2 = vop2;
2618 vop2->registered_num_wins = vop2_data->win_size;
2643 .name = "vop2",
2653 struct vop2 *vop2;
2662 /* Allocate vop2 struct and its vop2_win array */
2663 alloc_size = struct_size(vop2, win, vop2_data->win_size);
2664 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2665 if (!vop2)
2668 vop2->dev = dev;
2669 vop2->data = vop2_data;
2670 vop2->drm = drm;
2672 dev_set_drvdata(dev, vop2);
2676 drm_err(vop2->drm, "failed to get vop2 register byname\n");
2680 vop2->regs = devm_ioremap_resource(dev, res);
2681 if (IS_ERR(vop2->regs))
2682 return PTR_ERR(vop2->regs);
2683 vop2->len = resource_size(res);
2685 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
2686 if (IS_ERR(vop2->map))
2687 return PTR_ERR(vop2->map);
2689 ret = vop2_win_init(vop2);
2695 vop2->lut_regs = devm_ioremap_resource(dev, res);
2696 if (IS_ERR(vop2->lut_regs))
2697 return PTR_ERR(vop2->lut_regs);
2700 vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
2702 vop2->hclk = devm_clk_get(vop2->dev, "hclk");
2703 if (IS_ERR(vop2->hclk)) {
2704 drm_err(vop2->drm, "failed to get hclk source\n");
2705 return PTR_ERR(vop2->hclk);
2708 vop2->aclk = devm_clk_get(vop2->dev, "aclk");
2709 if (IS_ERR(vop2->aclk)) {
2710 drm_err(vop2->drm, "failed to get aclk source\n");
2711 return PTR_ERR(vop2->aclk);
2714 vop2->irq = platform_get_irq(pdev, 0);
2715 if (vop2->irq < 0) {
2716 drm_err(vop2->drm, "cannot find irq for vop2\n");
2717 return vop2->irq;
2720 mutex_init(&vop2->vop2_lock);
2722 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
2726 ret = vop2_create_crtcs(vop2);
2730 ret = vop2_find_rgb_encoder(vop2);
2732 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
2733 vop2->drm, ret);
2734 if (IS_ERR(vop2->rgb)) {
2735 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
2736 ret = PTR_ERR(vop2->rgb);
2739 vop2->rgb = NULL;
2743 rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
2750 vop2_destroy_crtcs(vop2);
2757 struct vop2 *vop2 = dev_get_drvdata(dev);
2761 if (vop2->rgb)
2762 rockchip_rgb_fini(vop2->rgb);
2764 vop2_destroy_crtcs(vop2);