Lines Matching +full:px30 +full:- +full:video +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
16 #include <linux/phy/phy.h>
21 #include <video/mipi_display.h>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
245 int (*dphy_rx_init)(struct phy *phy);
246 int (*dphy_rx_power_on)(struct phy *phy);
247 int (*dphy_rx_power_off)(struct phy *phy);
264 /* dual-channel */
269 struct phy *phy; member
272 /* being a phy for other mipi hosts */
275 struct phy *dphy;
355 return -EINVAL; in max_mbps_to_parameter()
360 writel(val, dsi->base + reg); in dsi_write()
386 * ns2bc - Nanoseconds to byte clock cycles
390 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
394 * ns2ui - Nanoseconds to UI time periods
398 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
406 if (dsi->phy) in dw_mipi_dsi_phy_init()
412 * 000 - between 80 and 200 MHz in dw_mipi_dsi_phy_init()
413 * 001 - between 200 and 300 MHz in dw_mipi_dsi_phy_init()
414 * 010 - between 300 and 500 MHz in dw_mipi_dsi_phy_init()
415 * 011 - between 500 and 700 MHz in dw_mipi_dsi_phy_init()
416 * 100 - between 700 and 900 MHz in dw_mipi_dsi_phy_init()
417 * 101 - between 900 and 1100 MHz in dw_mipi_dsi_phy_init()
418 * 110 - between 1100 and 1300 MHz in dw_mipi_dsi_phy_init()
419 * 111 - between 1300 and 1500 MHz in dw_mipi_dsi_phy_init()
421 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
423 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
425 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
427 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
431 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
433 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
453 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
455 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
461 * Only in this way can we get correct mipi phy pll frequency. in dw_mipi_dsi_phy_init()
466 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
512 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
522 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
524 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
528 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
529 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
536 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
548 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; in dw_mipi_dsi_get_lane_mbps()
556 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
557 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
559 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
561 dsi->format); in dw_mipi_dsi_get_lane_mbps()
565 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
572 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
576 /* for external phy only a the mipi_dphy_config is necessary */ in dw_mipi_dsi_get_lane_mbps()
577 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
578 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, in dw_mipi_dsi_get_lane_mbps()
580 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
581 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
582 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
587 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
606 * Due to the use of a "by 2 pre-scaler," the range of the in dw_mipi_dsi_get_lane_mbps()
620 delta = abs(fout - tmp); in dw_mipi_dsi_get_lane_mbps()
630 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
631 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
632 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
633 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
635 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
636 return -EINVAL; in dw_mipi_dsi_get_lane_mbps()
658 /* Table A-3 High-Speed Transition Times */
712 i--; in dw_mipi_dsi_phy_get_timing()
729 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
730 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
731 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
733 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
734 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
735 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
737 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
738 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
739 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
745 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
746 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
747 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
758 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
760 s->output_mode = ROCKCHIP_OUT_MODE_P888; in dw_mipi_dsi_encoder_atomic_check()
763 s->output_mode = ROCKCHIP_OUT_MODE_P666; in dw_mipi_dsi_encoder_atomic_check()
766 s->output_mode = ROCKCHIP_OUT_MODE_P565; in dw_mipi_dsi_encoder_atomic_check()
770 return -EINVAL; in dw_mipi_dsi_encoder_atomic_check()
773 s->output_type = DRM_MODE_CONNECTOR_DSI; in dw_mipi_dsi_encoder_atomic_check()
774 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
775 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; in dw_mipi_dsi_encoder_atomic_check()
785 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
786 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
795 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
797 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
802 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
803 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
805 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
817 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
820 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, in rockchip_dsi_drm_create_encoder()
821 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
840 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
842 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
847 match->compatible))) { in dw_mipi_dsi_rockchip_find_second()
851 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
858 /* same display device in port1-ep0 for both */ in dw_mipi_dsi_rockchip_find_second()
875 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
880 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
883 return &pdev->dev; in dw_mipi_dsi_rockchip_find_second()
909 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
910 "clock-master"); in dw_mipi_dsi_rockchip_bind()
911 master2 = of_property_read_bool(second->of_node, in dw_mipi_dsi_rockchip_bind()
912 "clock-master"); in dw_mipi_dsi_rockchip_bind()
915 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
916 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
920 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
921 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
924 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
926 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
930 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
931 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
933 return -ENODEV; in dw_mipi_dsi_rockchip_bind()
936 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
937 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
941 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
942 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
943 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
945 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
952 * With the GRF clock running, write lane and dual-mode configurations in dw_mipi_dsi_rockchip_bind()
957 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
959 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
964 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
965 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
967 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
974 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
975 dev->of_node, 0, 0); in dw_mipi_dsi_rockchip_bind()
977 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
983 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
988 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
990 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
991 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
992 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1003 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1006 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1008 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1010 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1012 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1013 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1014 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1029 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1031 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1032 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1033 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1034 return -EBUSY; in dw_mipi_dsi_rockchip_host_attach()
1037 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1038 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1040 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1042 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1065 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1066 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1067 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1081 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1083 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1084 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1085 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1101 * Just make the rest of Rockchip-DRM happy in dw_mipi_dsi_rockchip_dphy_bind()
1120 static int dw_mipi_dsi_dphy_init(struct phy *phy) in dw_mipi_dsi_dphy_init() argument
1122 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_init()
1125 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1127 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1128 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1129 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1130 return -EBUSY; in dw_mipi_dsi_dphy_init()
1133 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1134 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1136 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1140 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1141 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1145 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1147 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1151 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1152 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1153 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1161 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1163 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1164 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1165 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1170 static int dw_mipi_dsi_dphy_exit(struct phy *phy) in dw_mipi_dsi_dphy_exit() argument
1172 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_exit()
1174 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1176 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1177 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1178 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1183 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) in dw_mipi_dsi_dphy_configure() argument
1185 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; in dw_mipi_dsi_dphy_configure()
1186 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_configure()
1189 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in dw_mipi_dsi_dphy_configure()
1193 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1194 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1199 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) in dw_mipi_dsi_dphy_power_on() argument
1201 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_on()
1204 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1205 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1207 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1209 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1210 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1214 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1216 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1220 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1222 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1226 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1228 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1232 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1234 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1238 /* do soc-variant specific init */ in dw_mipi_dsi_dphy_power_on()
1239 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1240 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1242 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1261 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1262 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1267 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1269 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1271 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1273 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1277 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) in dw_mipi_dsi_dphy_power_off() argument
1279 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_off()
1282 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1284 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1288 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1289 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1291 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1294 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1295 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1297 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1316 * Re-configure DSI state, if we were previously initialized. We need in dw_mipi_dsi_rockchip_resume()
1317 * to do this before rockchip_drm_drv tries to re-enable() any panels. in dw_mipi_dsi_rockchip_resume()
1319 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1320 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1322 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1327 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1328 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1330 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1342 struct device *dev = &pdev->dev; in dw_mipi_dsi_rockchip_probe()
1343 struct device_node *np = dev->of_node; in dw_mipi_dsi_rockchip_probe()
1353 return -ENOMEM; in dw_mipi_dsi_rockchip_probe()
1356 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_rockchip_probe()
1357 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1359 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1364 if (cdata[i].reg == res->start) { in dw_mipi_dsi_rockchip_probe()
1365 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1372 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1373 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1374 return -EINVAL; in dw_mipi_dsi_rockchip_probe()
1378 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1379 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1380 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1385 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1386 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1387 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1392 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1393 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1394 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1396 * if external phy is present, pll will be in dw_mipi_dsi_rockchip_probe()
1399 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1401 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1409 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1410 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1411 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1412 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1419 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1420 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1421 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1422 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1428 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1429 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1431 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1434 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1435 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1436 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1437 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1438 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1439 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1442 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1444 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1445 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1446 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); in dw_mipi_dsi_rockchip_probe()
1447 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1450 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1455 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1456 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1457 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1458 if (ret != -EPROBE_DEFER) in dw_mipi_dsi_rockchip_probe()
1471 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1512 static int rk3399_dphy_tx1rx1_init(struct phy *phy) in rk3399_dphy_tx1rx1_init() argument
1514 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_init()
1520 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1522 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1524 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1532 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) in rk3399_dphy_tx1rx1_power_on() argument
1534 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_on()
1540 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1542 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1545 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1547 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1551 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1553 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1562 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1563 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1571 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) in rk3399_dphy_tx1rx1_power_off() argument
1573 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_off()
1575 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1655 .compatible = "rockchip,px30-mipi-dsi",
1658 .compatible = "rockchip,rk3288-mipi-dsi",
1661 .compatible = "rockchip,rk3399-mipi-dsi",
1664 .compatible = "rockchip,rk3568-mipi-dsi",
1677 .name = "dw-mipi-dsi-rockchip",
1679 * For dual-DSI display, one DSI pokes at the other DSI's