Lines Matching full:dsi
359 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
361 writel(val, dsi->base + reg); in dsi_write()
364 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
373 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
375 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
378 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
380 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
383 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
389 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
391 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
397 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2ui() argument
399 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
404 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_init() local
407 if (dsi->phy) in dw_mipi_dsi_phy_init()
422 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
424 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
426 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
428 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
432 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
434 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
438 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, in dw_mipi_dsi_phy_init()
444 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, in dw_mipi_dsi_phy_init()
446 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, in dw_mipi_dsi_phy_init()
450 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_phy_init()
453 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
454 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
455 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
456 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
464 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
466 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
467 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
469 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
472 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
474 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
477 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, in dw_mipi_dsi_phy_init()
481 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
484 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
489 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
490 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
491 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
492 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
493 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
494 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
495 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
496 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
497 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
498 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
499 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, in dw_mipi_dsi_phy_init()
500 BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
502 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
503 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
504 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
505 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); in dw_mipi_dsi_phy_init()
506 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
507 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
508 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
509 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
510 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
511 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
513 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
520 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_on() local
523 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
525 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
529 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
530 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
535 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_off() local
537 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
545 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_get_lane_mbps() local
557 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
558 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
560 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
562 dsi->format); in dw_mipi_dsi_get_lane_mbps()
573 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
578 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
581 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
582 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
583 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
588 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
631 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
632 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
633 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
634 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
636 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
728 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_config() argument
730 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
731 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
732 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
734 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
735 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
736 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
738 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
739 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
740 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
743 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_rockchip_set_lcdsel() argument
746 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
747 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
748 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
757 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
759 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
775 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
783 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
786 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
787 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
796 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
798 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
802 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); in dw_mipi_dsi_encoder_enable()
803 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
804 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
806 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
815 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, in rockchip_dsi_drm_create_encoder() argument
818 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
822 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
836 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_find_second() argument
841 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
843 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
852 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
899 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_bind() local
905 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_bind()
910 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
916 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
921 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
925 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
927 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
931 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
932 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
937 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
938 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
942 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
943 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
944 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
946 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
956 * commands over DSI. in dw_mipi_dsi_rockchip_bind()
958 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
960 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
964 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_bind()
965 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
966 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
968 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
970 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); in dw_mipi_dsi_rockchip_bind()
975 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
978 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
984 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
989 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
991 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
992 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
993 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1002 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_unbind() local
1004 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1007 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1009 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1011 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1013 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1014 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1015 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1026 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_attach() local
1030 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1032 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1033 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1034 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1038 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1039 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1041 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1043 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1048 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_attach()
1066 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1067 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1068 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1075 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_detach() local
1078 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_detach()
1082 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1084 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1085 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1086 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1123 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_init() local
1126 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1128 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1129 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1130 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1134 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1135 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1137 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1141 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1142 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1146 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1148 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1152 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1153 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1154 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1162 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1164 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1165 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1166 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1173 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_exit() local
1175 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1177 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1178 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1179 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1187 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_configure() local
1194 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1195 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1202 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_on() local
1205 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1206 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1208 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1210 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1211 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1215 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1217 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1221 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1223 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1227 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1229 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1233 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1235 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1240 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1241 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1243 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1252 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); in dw_mipi_dsi_dphy_power_on()
1253 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_dphy_power_on()
1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); in dw_mipi_dsi_dphy_power_on()
1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); in dw_mipi_dsi_dphy_power_on()
1257 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); in dw_mipi_dsi_dphy_power_on()
1260 dw_mipi_dsi_phy_write(dsi, 0x0, 0); in dw_mipi_dsi_dphy_power_on()
1262 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1263 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1268 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1270 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1272 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1274 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1280 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_off() local
1283 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1285 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1289 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1290 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1292 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1295 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1296 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1298 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1313 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_resume() local
1317 * Re-configure DSI state, if we were previously initialized. We need in dw_mipi_dsi_rockchip_resume()
1320 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1321 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1323 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1327 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_resume()
1328 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1329 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1331 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1345 struct dw_mipi_dsi_rockchip *dsi; in dw_mipi_dsi_rockchip_probe() local
1352 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_rockchip_probe()
1353 if (!dsi) in dw_mipi_dsi_rockchip_probe()
1357 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_rockchip_probe()
1358 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1359 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); in dw_mipi_dsi_rockchip_probe()
1360 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1366 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1373 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1374 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1379 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1380 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1381 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1386 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1387 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1388 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1393 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1394 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1395 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1400 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1402 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1410 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1411 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1412 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1413 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1420 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1421 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1422 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1423 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1429 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1430 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1432 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1435 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1436 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1437 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1438 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1439 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1440 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1441 platform_set_drvdata(pdev, dsi); in dw_mipi_dsi_rockchip_probe()
1443 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1445 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1446 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1448 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1451 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1456 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1457 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1458 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1470 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_remove() local
1472 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1515 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_init() local
1521 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1523 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1525 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1527 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1535 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_on() local
1538 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); in rk3399_dphy_tx1rx1_power_on()
1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1548 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1552 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1554 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1559 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in rk3399_dphy_tx1rx1_power_on()
1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1564 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1574 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_off() local
1576 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1656 .compatible = "rockchip,px30-mipi-dsi",
1659 .compatible = "rockchip,rk3288-mipi-dsi",
1662 .compatible = "rockchip,rk3399-mipi-dsi",
1665 .compatible = "rockchip,rk3568-mipi-dsi",
1678 .name = "dw-mipi-dsi-rockchip",
1680 * For dual-DSI display, one DSI pokes at the other DSI's